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MC145106P PDF预览

MC145106P

更新时间: 2024-11-06 04:59:27
品牌 Logo 应用领域
LANSDALE 光电二极管
页数 文件大小 规格书
8页 384K
描述
PLL Frequency Synthesizer CMOS

MC145106P 数据手册

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ML145106  
PLL Frequency Synthesizer  
CMOS  
INTERFACES WITH DUAL–MODULUS PRESCALERS  
Legacy Device: Motorola MC145106  
The ML145106 is a phase–locked loop (PLL) frequency synthesizer  
constructed in CMOS on a single monolithic structure. This synthesizer  
finds applications in such areas as AM radio, shortwave, amateur radio,  
CB and FM transceivers. The device contains an oscillator/amplifier, a  
210 or 211 divider chain for the oscillator signal, a programmable  
divider chain for the input signal, and a phase detector. The ML145106  
has circuitry for a 10.24 MHz oscillator or may operate with an exter-  
nal signal. The circuit provides a 5.12 MHz output signal, which can be  
used for frequency tripling. A 29 programmable divider divides the  
input signal frequency for channel selection. The inputs to the program-  
mable divider are standard ground–to–supply binary signals. Pull–down  
resistors on these inputs normally set these inputs to ground enabling  
these programmable inputs to be controlled from a mechanical switch  
or electronic circuitry.  
P DIP 18 = VP  
PLASTIC DIP  
CASE 707  
18  
1
SOG 20W = -6P  
SOG PACKAGE  
CASE 751D  
20  
1
CROSS REFERENCE/ORDERING INFORMATION  
PACKAGE  
MOTOROLA  
LANSDALE  
P DIP 18  
SOG 20W  
MC145106P  
ML145106VP  
MC145106DW ML145106-6P  
The phase detector may control a VCO and yields a high level signal  
when input frequency is low, and a low level signal when input fre-  
quency is high. An out–of–lock signal is provided from the on–chip  
lock detector with a “0” level for the out–of–lock condition.  
Note: Lansdale lead free (Pb) product, as it  
becomes available, will be identified by a part  
number prefix change from ML to MLE.  
• Single Power Supply  
• Wide Supply Range: 4.5 to 12 V  
• Provision for 10.24 MHz Crystal Oscillator  
• 5.12 MHz Output  
• Programmable Division Binary Input Selects up to 29  
• On–Chip Pull–Down Resistors on Programmable Divider Inputs  
• Selectable Reference Divider, 210 or 211 (Including ÷ 2)  
• Three–State Phase Detector  
• See Application Note AN535 and Article Reprint AR254  
• Chip Complexity: 880 FETs or 220 Equivalent Gates  
BLOCK DIAGRAM  
OSC  
out  
÷
2
FS  
out  
REFERENCE  
DIVIDE 2 OR 2  
φDet  
÷
2
out  
OSC  
in  
9
10  
PHASE  
DETECTOR  
9
f
LD  
DIVIDE–BY–N COUNTER 2 – 1  
in  
P0 P1 P2 P3 P4 P5 P6 P7 P8  
Page 1 of 8  
www.lansdale.com  
Issue bBC  

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