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MC145106L PDF预览

MC145106L

更新时间: 2024-11-29 12:59:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
8页 119K
描述
PLL/Frequency Synthesis Circuit, CMOS, CDIP18

MC145106L 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP18,.3Reach Compliance Code:unknown
风险等级:5.82JESD-30 代码:R-XDIP-T18
JESD-609代码:e0端子数量:18
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP18,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:4.5/12 V
认证状态:Not Qualified子类别:PLL or Frequency Synthesis Circuits
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC145106L 数据手册

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Order this document  
by MC145106/D  
SEMICONDUCTOR TECHNICAL DATA  
CMOS  
P SUFFIX  
PLASTIC DIP  
CASE 707  
The MC145106 is a phase–locked loop (PLL) frequency synthesizer  
constructed in CMOS on a single monolithic structure. This synthesizer finds  
applications in such areas as CB and FM transceivers. The device contains an  
18  
1
10  
11  
oscillator/amplifier, a 2  
or 2  
divider chain for the oscillator signal, a  
programmable divider chain for the input signal, and a phase detector. The  
MC145106 has circuitry for a 10.24 MHz oscillator or may operate with an  
external signal. The circuit provides a 5.12 MHz output signal, which can be  
DW SUFFIX  
SOG PACKAGE  
CASE 751D  
20  
9
used for frequency tripling. A 2 programmable divider divides the input signal  
1
frequency for channel selection. The inputs to the programmable divider are  
standard ground–to–supply binary signals. Pull–down resistors on these inputs  
normally set these inputs to ground enabling these programmable inputs to be  
controlled from a mechanical switch or electronic circuitry.  
The phase detector may control a VCO and yields a high level signal when  
input frequency is low, and a low level signal when input frequency is high. An  
out–of–lock signal is provided from the on–chip lock detector with a “0” level for  
the out–of–lock condition.  
ORDERING INFORMATION  
MC145106P  
Plastic DIP  
MC145106DW  
SOG Package  
Single Power Supply  
Wide Supply Range: 4.5 to 12 V  
Provision for 10.24 MHz Crystal Oscillator  
5.12 MHz Output  
Programmable Division Binary Input Selects up to 2  
On–Chip Pull–Down Resistors on Programmable Divider Inputs  
Selectable Reference Divider, 2 or 2 (Including ÷ 2)  
Three–State Phase Detector  
See Application Note AN535 and Article Reprint AR254  
Chip Complexity: 880 FETs or 220 Equivalent Gates  
See the MC145151–2 and MC145152–2 for Higher Performance and  
Added Flexibility  
9
10  
11  
BLOCK DIAGRAM  
OSC  
out  
÷
2
FS  
out  
REFERENCE  
DIVIDE 2 OR 2  
φDet  
÷
2
out  
OSC  
in  
9
10  
PHASE  
DETECTOR  
9
f
LD  
DIVIDE–BY–N COUNTER 2 – 1  
in  
P0 P1 P2 P3 P4 P5 P6 P7 P8  
REV 3  
1/98  
Motorola, Inc. 1998  

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