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MC14504BFL1 PDF预览

MC14504BFL1

更新时间： 2024-11-29 21:13:39
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件接口集成电路锁存器
页数 文件大小 规格书
8页 188K
描述
HEX TTL/CMOS TO CMOS TRANSLATOR, TRUE OUTPUT, PDSO16, EIAJ, PLASTIC, SOIC-16

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MC14504BFL1 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP16,.3
针数：16Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.66最大延迟：550 ns
接口集成电路类型：TTL/CMOS TO CMOS TRANSLATORJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：10.2 mm
位数：1功能数量：6
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出锁存器或寄存器：NONE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：5/15 V
认证状态：Not Qualified座面最大高度：2.05 mm
子类别：Level Translators最大供电电压：18 V
最小供电电压：3 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：5.275 mmBase Number Matches：1

MC14504BFL1 数据手册

 浏览型号MC14504BFL1的Datasheet PDF文件第2页浏览型号MC14504BFL1的Datasheet PDF文件第3页浏览型号MC14504BFL1的Datasheet PDF文件第4页浏览型号MC14504BFL1的Datasheet PDF文件第5页浏览型号MC14504BFL1的Datasheet PDF文件第6页浏览型号MC14504BFL1的Datasheet PDF文件第7页 
The MC14504B is a hex non–inverting level shifter using CMOS  
technology. The level shifter will shift a TTL signal to CMOS logic  
levels for any CMOS supply voltage between 5 and 15 volts. A control  
input also allows interface from CMOS to CMOS at one logic level to  
another logic level: Either up or down level translating is  
accomplished by selection of power supply levels V and V . The  
http://onsemi.com  
MARKING  
DIAGRAMS  
DD  
CC  
V
CC  
level sets the input signal levels while V  
selects the output  
DD  
voltage levels.  
16  
PDIP–16  
P SUFFIX  
CASE 648  
• UP Translates from a Low to a High Voltage or DOWN Translates  
from a High to a Low Voltage  
MC14504BCP  
AWLYYWW  
• Input Threshold Can Be Shifted for TTL Compatibility  
1
• No Sequencing Required on Power Supplies or Inputs for Power Up  
or Power Down  
16  
SOIC–16  
D SUFFIX  
CASE 751B  
14504B  
AWLYWW  
• 3 to 18 Vdc Operation for V and V  
• Diode Protected Inputs to V  
DD  
SS  
CC  
1
• Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
16  
TSSOP–16  
DT SUFFIX  
CASE 948F  
14  
504B  
ALYW  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)  
SS  
1
Symbol  
Parameter  
Value  
Unit  
V
16  
1
V
V
DC Supply Voltage Range  
DC Supply Voltage Range  
–0.5 to +18.0  
–0.5 to +18.0  
–0.5 to +18.0  
CC  
DD  
SOEIAJ–16  
F SUFFIX  
CASE 966  
V
MC14504B  
AWLYWW  
V
Input Voltage Range  
(DC or Transient)  
V
in  
V
Output Voltage Range  
(DC or Transient)  
–0.5 to V + 0.5  
V
out  
DD  
A
= Assembly Location  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
mW  
P
Power Dissipation,  
500  
D
per Package (Note 3.)  
ORDERING INFORMATION  
T
A
Ambient Temperature Range  
Storage Temperature Range  
–55 to +125  
–65 to +150  
260  
°C  
°C  
°C  
Device  
Package  
PDIP–16  
SOIC–16  
Shipping  
T
stg  
MC14504BCP  
MC14504BD  
2000/Box  
48/Rail  
T
L
Lead Temperature  
(8–Second Soldering)  
2. Maximum Ratings are those values beyond which damage to the device  
may occur.  
MC14504BDR2  
SOIC–16 2500/Tape & Reel  
3. Temperature Derating:  
MC14504BDT  
MC14504BF  
TSSOP–16  
SOEIAJ–16  
SOEIAJ–16  
96/Rail  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
See Note 1.  
See Note 1.  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
MC14504BFEL  
high–impedancecircuit. For proper operation, V and V should be constrained  
in  
out  
1. For ordering information on the EIAJ version of  
the SOIC packages, please contact your local  
ON Semiconductor representative.  
to the range V  
(V or V  
)
V
DD  
.
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 3  
MC14504B/D  
12345678

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