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MC14504BDTR2 PDF预览

MC14504BDTR2

更新时间： 2024-09-15 04:59:31
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 106K
描述
Hex Level Shifter for TTL to CMOS or CMOS to CMOS

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中文翻译

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MC14504BDTR2 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP16,.25
针数：16Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.14最大延迟：550 ns
接口集成电路类型：TTL/CMOS TO CMOS TRANSLATORJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
湿度敏感等级：1位数：1
功能数量：6端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出锁存器或寄存器：NONE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：5/15 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Level Translators
最大供电电压：18 V最小供电电压：3 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：4.4 mm
Base Number Matches：1

MC14504BDTR2 数据手册

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MC14504B  
Hex Level Shifter for TTL to  
CMOS or CMOS to CMOS  
The MC14504B is a hex non−inverting level shifter using CMOS  
technology. The level shifter will shift a TTL signal to CMOS logic  
levels for any CMOS supply voltage between 5 and 15 volts. A control  
input also allows interface from CMOS to CMOS at one logic level to  
another logic level: Either up or down level translating is  
http://onsemi.com  
MARKING  
accomplished by selection of power supply levels V and V . The  
DD  
CC  
DIAGRAMS  
V
CC  
level sets the input signal levels while V  
selects the output  
DD  
voltage levels.  
16  
1
PDIP−16  
P SUFFIX  
CASE 648  
MC14504BCP  
AWLYYWWG  
Features  
• UP Translates from a Low to a High Voltage or DOWN Translates  
from a High to a Low Voltage  
• Input Threshold Can Be Shifted for TTL Compatibility  
• No Sequencing Required on Power Supplies or Inputs for Power Up  
or Power Down  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
14504BG  
AWLYWW  
• 3 to 18 Vdc Operation for V and V  
DD  
SS  
CC  
1
• Diode Protected Inputs to V  
• Capable of Driving Two Low−Power TTL Loads or One Low−Power  
Schottky TTL Load Over the Rated Temperature Range  
• Pb−Free Packages are Available*  
16  
14  
504B  
ALYW  
TSSOP−16  
DT SUFFIX  
CASE 948F  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
1
Symbol  
Parameter  
DC Supply Voltage Range  
DC Supply Voltage Range  
Value  
Unit  
V
V
V
−0.5 to +18.0  
−0.5 to +18.0  
−0.5 to +18.0  
CC  
DD  
16  
1
V
SOEIAJ−16  
F SUFFIX  
CASE 966  
V
in  
Input Voltage Range  
(DC or Transient)  
V
MC14504B  
ALYWG  
V
out  
Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
I , I  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
mW  
in out  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
P
T
Power Dissipation, per Package  
(Note 1)  
500  
D
WW, W = Work Week  
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
A
G
= Pb−Free Indicator  
T
stg  
T
Lead Temperature  
(8−Second Soldering)  
L
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
*For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
in  
out  
to the range V v (V or V ) v V  
.
DD  
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 6  
MC14504B/D  
 
12345678

中文翻译

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MC14504BDTR2 替代型号

型号 品牌 替代类型 描述 数据表
MC14504BDT ONSEMI

完全替代

 Hex Level Shifter for TTL to CMOS or COMS to CMOS

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