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MC14504BD PDF预览

MC14504BD

更新时间: 2024-11-30 22:36:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
5页 192K
描述
Hex Level Shifter for TTL to CMOS or CMOS to CMOS

MC14504BD 技术参数

生命周期:Transferred零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.1
最大延迟:370 ns接口集成电路类型:TTL/CMOS TO CMOS TRANSLATOR
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm位数:1
功能数量:6端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出锁存器或寄存器:NONE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:5/15 V
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Level Translators最大供电电压:18 V
最小供电电压:3 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

MC14504BD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14504B is a hex non–inverting level shifter using CMOS  
technology. The level shifter will shift a TTL signal to CMOS logic levels for  
any CMOS supply voltage between 5 and 15 volts. A control input also  
allows interface from CMOS to CMOS at one logic level to another logic  
level: Either up or down level translating is accomplished by selection of  
P SUFFIX  
PLASTIC  
CASE 648  
power supply levels V  
and V . The V level sets the input signal levels  
DD  
CC CC  
while V  
DD  
selects the output voltage levels.  
UP Translates from a Low to a High Voltage or DOWN Translates from  
a High to a Low Voltage  
Input Threshold Can Be Shifted for TTL Compatibility  
No Sequencing Required on Power Supplies or Inputs for Power Up or  
Power Down  
D SUFFIX  
SOIC  
CASE 751B  
ORDERING INFORMATION  
3 to 18 Vdc Operation for V  
DD  
and V  
CC  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
Diode Protected Inputs to V  
SS  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
T
= – 55° to 125°C for all packages.  
A
LOGIC DIAGRAM  
PIN ASSIGNMENT  
V
V
DD  
V
1
2
16  
15  
V
CC  
CC  
DD  
A
F
out  
out  
A
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
F
in  
in  
LEVEL  
SHIFTER  
INPUT  
MODE  
OUTPUT  
B
MODE  
out  
B
E
E
in  
out  
C
out  
in  
TTL/CMOS  
MODE SELECT  
C
in  
D
out  
in  
V
D
SS  
Input Logic  
Levels  
Output Logic  
Levels  
Mode Select  
This device contains circuitry to protect  
the inputs against damage due to high static  
voltages or electric fields referenced to the  
1 (V  
)
TTL  
CMOS  
CMOS  
CC  
0 (V  
)
CMOS  
SS  
V
SS  
pin, only. Extra precautions must be  
taken to avoid applications of any voltage  
higher than maximum rated voltages to this  
high–impedance circuit. For proper opera-  
1/6 of package shown.  
tion, the ranges V  
V
18 V and V  
SS  
SS  
in  
V
out  
V
DD  
are recommended.  
Unused inputs must always be tied to an  
appropriate logic voltage level (e.g., either  
V or V ). Unused outputs must be left  
SS DD  
open.  
REV 3  
1/94  
Motorola, Inc. 1995  

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