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MC14504BCPS PDF预览

MC14504BCPS

更新时间: 2024-12-01 13:11:15
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摩托罗拉 - MOTOROLA /
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5页 192K
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MC14504BCPS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14504B is a hex non–inverting level shifter using CMOS  
technology. The level shifter will shift a TTL signal to CMOS logic levels for  
any CMOS supply voltage between 5 and 15 volts. A control input also  
allows interface from CMOS to CMOS at one logic level to another logic  
level: Either up or down level translating is accomplished by selection of  
P SUFFIX  
PLASTIC  
CASE 648  
power supply levels V  
and V . The V level sets the input signal levels  
DD  
CC CC  
while V  
DD  
selects the output voltage levels.  
UP Translates from a Low to a High Voltage or DOWN Translates from  
a High to a Low Voltage  
Input Threshold Can Be Shifted for TTL Compatibility  
No Sequencing Required on Power Supplies or Inputs for Power Up or  
Power Down  
D SUFFIX  
SOIC  
CASE 751B  
ORDERING INFORMATION  
3 to 18 Vdc Operation for V  
DD  
and V  
CC  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
Diode Protected Inputs to V  
SS  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
T
= – 55° to 125°C for all packages.  
A
LOGIC DIAGRAM  
PIN ASSIGNMENT  
V
V
DD  
V
1
2
16  
15  
V
CC  
CC  
DD  
A
F
out  
out  
A
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
F
in  
in  
LEVEL  
SHIFTER  
INPUT  
MODE  
OUTPUT  
B
MODE  
out  
B
E
E
in  
out  
C
out  
in  
TTL/CMOS  
MODE SELECT  
C
in  
D
out  
in  
V
D
SS  
Input Logic  
Levels  
Output Logic  
Levels  
Mode Select  
This device contains circuitry to protect  
the inputs against damage due to high static  
voltages or electric fields referenced to the  
1 (V  
)
TTL  
CMOS  
CMOS  
CC  
0 (V  
)
CMOS  
SS  
V
SS  
pin, only. Extra precautions must be  
taken to avoid applications of any voltage  
higher than maximum rated voltages to this  
high–impedance circuit. For proper opera-  
1/6 of package shown.  
tion, the ranges V  
V
18 V and V  
SS  
SS  
in  
V
out  
V
DD  
are recommended.  
Unused inputs must always be tied to an  
appropriate logic voltage level (e.g., either  
V or V ). Unused outputs must be left  
SS DD  
open.  
REV 3  
1/94  
Motorola, Inc. 1995  

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