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MC14504BCPG PDF预览

MC14504BCPG

更新时间: 2024-09-14 04:59:31
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器驱动程序和接口锁存器接口集成电路光电二极管PC
页数 文件大小 规格书
8页 106K
描述
Hex Level Shifter for TTL to CMOS or CMOS to CMOS

MC14504BCPG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:DIP
包装说明:LEAD FREE, PLASTIC, DIP-16针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.14
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:758017Samacsys Pin Count:16
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Dual-In-Line Packages
Samacsys Footprint Name:PDIP-16Samacsys Released Date:2020-03-16 03:06:38
Is Samacsys:N最大延迟:550 ns
接口集成电路类型:TTL/CMOS TO CMOS TRANSLATORJESD-30 代码:R-PDIP-T16
JESD-609代码:e3长度:19.175 mm
位数:1功能数量:6
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出锁存器或寄存器:NONE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):260电源:5/15 V
认证状态:Not Qualified座面最大高度:4.44 mm
子类别:Level Translators最大供电电压:18 V
最小供电电压:3 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Matte Tin (Sn) - annealed
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.62 mmBase Number Matches:1

MC14504BCPG 数据手册

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MC14504B  
Hex Level Shifter for TTL to  
CMOS or CMOS to CMOS  
The MC14504B is a hex non−inverting level shifter using CMOS  
technology. The level shifter will shift a TTL signal to CMOS logic  
levels for any CMOS supply voltage between 5 and 15 volts. A control  
input also allows interface from CMOS to CMOS at one logic level to  
another logic level: Either up or down level translating is  
http://onsemi.com  
MARKING  
accomplished by selection of power supply levels V and V . The  
DD  
CC  
DIAGRAMS  
V
CC  
level sets the input signal levels while V  
selects the output  
DD  
voltage levels.  
16  
1
PDIP−16  
P SUFFIX  
CASE 648  
MC14504BCP  
AWLYYWWG  
Features  
UP Translates from a Low to a High Voltage or DOWN Translates  
from a High to a Low Voltage  
Input Threshold Can Be Shifted for TTL Compatibility  
No Sequencing Required on Power Supplies or Inputs for Power Up  
or Power Down  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
14504BG  
AWLYWW  
3 to 18 Vdc Operation for V and V  
DD  
SS  
CC  
1
Diode Protected Inputs to V  
Capable of Driving Two Low−Power TTL Loads or One Low−Power  
Schottky TTL Load Over the Rated Temperature Range  
Pb−Free Packages are Available*  
16  
14  
504B  
ALYW  
TSSOP−16  
DT SUFFIX  
CASE 948F  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
1
Symbol  
Parameter  
DC Supply Voltage Range  
DC Supply Voltage Range  
Value  
Unit  
V
V
V
0.5 to +18.0  
0.5 to +18.0  
0.5 to +18.0  
CC  
DD  
16  
1
V
SOEIAJ−16  
F SUFFIX  
CASE 966  
V
in  
Input Voltage Range  
(DC or Transient)  
V
MC14504B  
ALYWG  
V
out  
Output Voltage Range  
(DC or Transient)  
0.5 to V + 0.5  
V
DD  
I , I  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
mW  
in out  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
P
T
Power Dissipation, per Package  
(Note 1)  
500  
D
WW, W = Work Week  
Ambient Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
A
G
= Pb−Free Indicator  
T
stg  
T
Lead Temperature  
(8−Second Soldering)  
L
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
*For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
in  
out  
to the range V v (V or V ) v V  
.
DD  
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 6  
MC14504B/D  
 

MC14504BCPG 替代型号

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CD4504BF3A TI

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