The MC14504B is a hex non–inverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to
another logic level: Either up or down level translating is
accomplished by selection of power supply levels V and V . The
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MARKING
DIAGRAMS
DD
CC
V
CC
level sets the input signal levels while V
selects the output
DD
voltage levels.
16
PDIP–16
P SUFFIX
CASE 648
• UP Translates from a Low to a High Voltage or DOWN Translates
from a High to a Low Voltage
MC14504BCP
AWLYYWW
• Input Threshold Can Be Shifted for TTL Compatibility
1
• No Sequencing Required on Power Supplies or Inputs for Power Up
or Power Down
16
SOIC–16
D SUFFIX
CASE 751B
14504B
AWLYWW
• 3 to 18 Vdc Operation for V and V
• Diode Protected Inputs to V
DD
SS
CC
1
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
16
TSSOP–16
DT SUFFIX
CASE 948F
14
504B
ALYW
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
1
Symbol
Parameter
Value
Unit
V
16
1
V
V
DC Supply Voltage Range
DC Supply Voltage Range
–0.5 to +18.0
–0.5 to +18.0
–0.5 to +18.0
CC
DD
SOEIAJ–16
F SUFFIX
CASE 966
V
MC14504B
AWLYWW
V
Input Voltage Range
(DC or Transient)
V
in
V
Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
out
DD
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
mW
P
Power Dissipation,
500
D
per Package (Note 3.)
ORDERING INFORMATION
T
A
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
Device
Package
PDIP–16
SOIC–16
Shipping
T
stg
MC14504BCP
MC14504BD
2000/Box
48/Rail
T
L
Lead Temperature
(8–Second Soldering)
2. Maximum Ratings are those values beyond which damage to the device
may occur.
MC14504BDR2
SOIC–16 2500/Tape & Reel
3. Temperature Derating:
MC14504BDT
MC14504BF
TSSOP–16
SOEIAJ–16
SOEIAJ–16
96/Rail
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
See Note 1.
See Note 1.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14504BFEL
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14504B/D