The MC14503B is a hex non–inverting buffer with 3–state outputs,
and a high current source and sink capability. The 3–state outputs
make it useful in common bussing applications. Two disable controls
are provided. A high level on the Disable A input causes the outputs of
buffers 1 through 4 to go into a high impedance state and a high level
on the Disable B input causes the outputs of buffers 5 and 6 to go into a
high impedance state.
http://onsemi.com
MARKING
DIAGRAMS
16
• 3–State Outputs
• TTL Compatible — Will Drive One TTL Load Over Full
Temperature Range
PDIP–16
P SUFFIX
CASE 648
MC14503BCP
AWLYYWW
1
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Two Disable Controls for Added Versatility
• Pin for Pin Replacement for MM80C97 and 340097
16
SOIC–16
D SUFFIX
CASE 751B
14503B
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
16
Symbol
Parameter
Value
Unit
V
SOEIAJ–16
F SUFFIX
CASE 966
MC14503B
AWLYWW
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
1
A
= Assembly Location
I
Input Current
(DC or Transient) per Pin
±10
±25
500
mA
mA
mW
in
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
I
Output Current
(DC or Transient) per Pin
out
P
Power Dissipation,
D
per Package (Note 3.)
ORDERING INFORMATION
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
Device
Package
PDIP–16
SOIC–16
Shipping
T
stg
MC14503BCP
MC14503BD
2000/Box
48/Rail
T
Lead Temperature
(8–Second Soldering)
L
MC14503BDR2
SOIC–16 2500/Tape & Reel
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
MC14503BF
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
MC14503BFEL
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14503B/D