Order this document
by MC145003/D
SEMICONDUCTOR TECHNICAL DATA
Product Preview
CMOS
TheMC145003/5004are128–segment, multiplexed–by–fourLCDDrivers.
The two devices are functionally the same except for their data input proto-
cols. The MC145003 uses an SPI data input protocol which is directly com-
patible with that of the MC6805 family of microcomputers. Using a minimal
amount of software (see example), the device may be interfaced to the
MC68HCXX product families. The MC145004 has a IIC interface and has es-
sentially the same protocol, except that the device sends an acknowledge bit
back to the transmitter after each eight–bit byte is received. MC145004 also
has a “read mode”, whereby data sent to the device may be retrieved via the
IIC bus.
QFP
FU SUFFIX
CASE 848B
1
52
ORDERING INFORMATION
MC145003FU
MC145004FU
QFP
QFP
The MC145003/MC145004 drives the liquid–crystal displays in a multi-
plexed–by–four configuration. The device accepts data from a microproces-
sor or other serial data source to drive one segment per bit. The chip does not
have a decoder, allowing for the flexibility of formatting the segment data
externally.
PIN ASSIGNMENT
Devices are independently addressable via a two–wire (or three–wire)
communication link which can be common with other MC145003/MC145004
and/or other peripheral devices.
52 51 50 49 48 47 46 45 44 43 42 41 40
FP32
FP31
FP30
FP29
FP28
FP27
FP26
FP25
FP24
FP23
FP22
FP21
FP20
1
2
3
4
5
6
7
8
39
38
37
36
35
34
33
32
31
30
29
28
27
D
in
DCLK
FS
•
•
•
Drives 128 Segments Per Package
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FP8
FP9
FP10
Devices May Be Cascaded for Larger LCD Applications
May Be Used with the Following LCDs: Segmented Alphanumeric,
Bar Graph, Dot Matrix, Custom
•
•
•
•
Quiscent Supply Current: 85 µA @ 2.8 V V
Operating Voltage Range: 2.8 to 5.5 V
Operating Temperature Range: –40 to 85°C
Separate Access to LCD Drive Section’s Supply Voltage to Allow for
Temperature Compensation
DD
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
•
See Application Notes AN1066 and AN442
BLOCK DIAGRAM
BP1–BP4
FP1–FP32
DRIVERS
NC = NO CONNECTION
V
LCD
OSC1
OSC2
OSCILLATOR
DRIVERS
FRAME
SYNC
GENERATOR
FS
LCD VOLTAGE
WAVEFORM
AND TIMING
GENERATOR
128 – 32
MULTIPLEX
POR
DCLK
D
in
128–BIT LATCH
A0
A1
A2
ENB
128–BIT SHIFT REGISTER
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
12/94
Motorola, Inc. 1994