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MC14093BCP

更新时间： 2024-11-22 22:58:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 226K
描述
Quad 2-Input NAND Schmitt Trigger

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中文翻译

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MC14093BCP 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：PLASTIC, DIP-14Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.66
系列：4000/14000/40000JESD-30 代码：R-PDIP-T14
JESD-609代码：e0长度：18.86 mm
负载电容（CL）：50 pF逻辑集成电路类型：NAND GATE
最大I（ol）：0.0042 A功能数量：4
输入次数：2端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP14,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5/15 V
Prop。Delay @ Nom-Sup：250 ns传播延迟（tpd）：250 ns
认证状态：Not Qualified施密特触发器：YES
座面最大高度：4.69 mm子类别：Gates
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

MC14093BCP 数据手册

 浏览型号MC14093BCP的Datasheet PDF文件第2页浏览型号MC14093BCP的Datasheet PDF文件第3页浏览型号MC14093BCP的Datasheet PDF文件第4页浏览型号MC14093BCP的Datasheet PDF文件第5页浏览型号MC14093BCP的Datasheet PDF文件第6页 
SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 632  
The MC14093B Schmitt trigger is constructed with MOS P–channel and  
N–channel enhancement mode devices in a single monolithic structure.  
These devices find primary use where low power dissipation and/or high  
noise immunity is desired. The MC14093B may be used in place of the  
MC14011B quad 2–input NAND gate for enhanced noise immunity or to  
“square up” slowly changing waveforms.  
P SUFFIX  
PLASTIC  
CASE 646  
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
Triple Diode Protection on All Inputs  
Pin–for–Pin Compatible with CD4093  
Can be Used to Replace MC14011B  
D SUFFIX  
SOIC  
CASE 751A  
•
•
•
•
ORDERING INFORMATION  
Independent Schmitt–Trigger at each Input  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
T
A
= – 55° to 125°C for all packages.  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
DD  
– 0.5 to + 18.0  
V , V  
in out  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
LOGIC DIAGRAM  
I , I  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
1
3
2
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
5
4
6
T
stg  
– 65 to + 150  
260  
T
Lead Temperature (8–Second Soldering)  
C
L
8
9
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
10  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
12  
11  
13  
EQUIVALENT CIRCUIT SCHEMATIC  
V
V
= PIN 14  
= PIN 7  
DD  
SS  
(1/4 OF CIRCUIT SHOWN)  
This device contains protection circuitry to guard against damage  
due to high static voltages or electric fields. However, precautions must  
be taken to avoid applications of any voltage higher than maximum rated  
voltages to this high-impedance circuit. For proper operation, V and  
in  
V
out  
should be constrained to the range V  
SS  
≤ (V or V ) ≤ V .  
in out DD  
Unused inputs must always be tied to an appropriate logic voltage  
level (e.g., either V or V ). Unused outputs must be left open.  
SS DD  
REV 3  
1/94  
Motorola, Inc. 1995  
123456

中文翻译

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