Datasheet > 逻辑 > 栅极> MC14075BCL

MC14075BCL

更新时间： 2024-11-20 04:59:31

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		栅
页数	文件大小	规格书
11页	330K
描述
B-Suffix Series CMOS Gates

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MC14075BCL 数据手册

SEMICONDUCTOR TECHNICAL DATA

The B Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure (Complemen-

tary MOS). Their primary use is where low power dissipation and/or high

noise immunity is desired.

•

Supply Voltage Range = 3.0 Vdc to 18 Vdc

All Outputs Buffered

Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range.

Double Diode Protection on All Inputs Except: Triple Diode Protection

on MC14011B and MC14081B

Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix

Devices (Exceptions: MC14068B and MC14078B)

•

L SUFFIX

CERAMIC

CASE 632

P SUFFIX

PLASTIC

CASE 646

D SUFFIX

SOIC

CASE 751A

ORDERING INFORMATION

MC14XXXBCP

MC14XXXBCL

MC14XXXBD

Plastic

Ceramic

SOIC

= – 55° to 125°C for all packages.

MAXIMUM RATINGS* (Voltages Referenced to V

)

Symbol

Parameter

DC Supply Voltage

Value

Unit

– 0.5 to + 18.0

V , V

Input or Output Voltage (DC or Transient)

– 0.5 to V

+ 0.5

in out

l , l

Input or Output Current (DC or Transient),

per Pin

± 10

in out

Power Dissipation, per Package†

Storage Temperature

500

stg

– 65 to + 150

260

Lead Temperature (8–Second Soldering)

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must

be taken to avoid applications of any voltage higher than maximum rated

voltages to this high-impedance circuit. For proper operation, V and

out

should be constrained to the range V

≤ (V or V ) ≤ V .

in out DD

Unused inputs must always be tied to an appropriate logic voltage

level (e.g., either V or V ). Unused outputs must be left open.

SS DD

REV 3

1/94

Motorola, Inc. 1995

MOTOROLA CMOS LOGIC DATA

MC14001B

12 3 4 5 6 7...11

中文翻译

下载PDF

与MC14075BCL相关器件

型号	品牌	获取价格	描述	数据表
MC14075BCLD	MOTOROLA	获取价格	4000/14000/40000 SERIES, TRIPLE 3-INPUT OR GATE, CDIP14, 632-08
MC14075BCLDS	MOTOROLA	获取价格	OR Gate, 4000/14000/40000 Series, 3-Func, 3-Input, CMOS, CDIP14, 632-08
MC14075BCP	MOTOROLA	获取价格	B-Suffix Series CMOS Gates
MC14075BCPD	MOTOROLA	获取价格	4000/14000/40000 SERIES, TRIPLE 3-INPUT OR GATE, PDIP14, PLASTIC, DIP-14
MC14075BCPDS	MOTOROLA	获取价格	暂无描述
MC14075BCPS	MOTOROLA	获取价格	OR Gate, CMOS, PDIP14
MC14075BD	MOTOROLA	获取价格	B-Suffix Series CMOS Gates
MC14075BDCBS	MOTOROLA	获取价格	OR Gate, CMOS, CDIP14
MC14075BDR2	MOTOROLA	获取价格	4000/14000/40000 SERIES, TRIPLE 3-INPUT OR GATE, PDSO14, PLASTIC, SOIC-14
MC14076B	ONSEMI	获取价格	4-Bit D-Type Register with Three-State Outputs