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MC14073B

更新时间： 2024-11-03 22:58:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 栅
页数 文件大小 规格书
11页 330K
描述
B-Suffix Series CMOS Gates

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MC14073B 数据手册

 浏览型号MC14073B的Datasheet PDF文件第2页浏览型号MC14073B的Datasheet PDF文件第3页浏览型号MC14073B的Datasheet PDF文件第4页浏览型号MC14073B的Datasheet PDF文件第5页浏览型号MC14073B的Datasheet PDF文件第6页浏览型号MC14073B的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
The B Series logic gates are constructed with P and N channel  
enhancement mode devices in a single monolithic structure (Complemen-  
tary MOS). Their primary use is where low power dissipation and/or high  
noise immunity is desired.  
•
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
All Outputs Buffered  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range.  
Double Diode Protection on All Inputs Except: Triple Diode Protection  
on MC14011B and MC14081B  
Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix  
Devices (Exceptions: MC14068B and MC14078B)  
•
•
L SUFFIX  
CERAMIC  
CASE 632  
P SUFFIX  
PLASTIC  
CASE 646  
D SUFFIX  
SOIC  
CASE 751A  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
T
A
= – 55° to 125°C for all packages.  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
DD  
– 0.5 to + 18.0  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
l , l  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
T
stg  
– 65 to + 150  
260  
T
Lead Temperature (8–Second Soldering)  
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
This device contains protection circuitry to guard against damage  
due to high static voltages or electric fields. However, precautions must  
be taken to avoid applications of any voltage higher than maximum rated  
voltages to this high-impedance circuit. For proper operation, V and  
in  
V
out  
should be constrained to the range V  
SS  
≤ (V or V ) ≤ V .  
in out DD  
Unused inputs must always be tied to an appropriate logic voltage  
level (e.g., either V or V ). Unused outputs must be left open.  
SS DD  
REV 3  
1/94  
Motorola, Inc. 1995  
1234567...11

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与MC14073B相关器件

型号 品牌 获取价格 描述 数据表
MC14073BAL MOTOROLA

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 		AND Gate, 4000/14000/40000 Series, 3-Func, 3-Input, CMOS, CDIP14, 632-08
MC14073BALD MOTOROLA

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 		AND Gate, 4000/14000/40000 Series, 3-Func, 3-Input, CMOS, CDIP14, 632-08
MC14073BALDS MOTOROLA

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 		4000/14000/40000 SERIES, TRIPLE 3-INPUT AND GATE, CDIP14, 632-08
MC14073BCL MOTOROLA

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 		B-Suffix Series CMOS Gates
MC14073BCLD MOTOROLA

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 		4000/14000/40000 SERIES, TRIPLE 3-INPUT AND GATE, CDIP14, 632-08
MC14073BCLDS MOTOROLA

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 		4000/14000/40000 SERIES, TRIPLE 3-INPUT AND GATE, CDIP14, 632-08
MC14073BCLG MOTOROLA

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 		NAND Gate, 4000/14000/40000 Series, 3-Func, 3-Input, CMOS, CDIP14, LEAD FREE, CERAMIC, DIP
MC14073BCLS MOTOROLA

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 		IC,LOGIC GATE,3 3-INPUT AND,CMOS,DIP,14PIN,CERAMIC
MC14073BCP ONSEMI

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 		B-SUFFIX SERIES CMOS GATES
MC14073BCP MOTOROLA

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 		B-Suffix Series CMOS Gates

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