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MC14053BFELG PDF预览

MC14053BFELG

更新时间： 2024-11-24 04:59:31
品牌 Logo 应用领域
安森美 - ONSEMI 解复用器开关复用器或开关信号电路光电二极管
页数 文件大小 规格书
12页 172K
描述
Analog Multiplexers/Demultiplexers

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MC14053BFELG 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：LEAD FREE, PLASTIC, EIAJ, SOP-16针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：7.73Is Samacsys：N
模拟集成电路 - 其他类型：SINGLE-ENDED MULTIPLEXERJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：10.2 mm
湿度敏感等级：3信道数量：2
功能数量：3端子数量：16
标称断态隔离度：50 dB通态电阻匹配规范：25 Ω
最大通态电阻 (Ron)：1050 Ω最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：5/15 V
认证状态：Not Qualified座面最大高度：2.05 mm
最大信号电流：0.025 A子类别：Multiplexer or Switches
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
最长断开时间：550 ns最长接通时间：550 ns
切换：BREAK-BEFORE-MAKE技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：5.275 mmBase Number Matches：1

MC14053BFELG 数据手册

 浏览型号MC14053BFELG的Datasheet PDF文件第2页浏览型号MC14053BFELG的Datasheet PDF文件第3页浏览型号MC14053BFELG的Datasheet PDF文件第4页浏览型号MC14053BFELG的Datasheet PDF文件第5页浏览型号MC14053BFELG的Datasheet PDF文件第6页浏览型号MC14053BFELG的Datasheet PDF文件第7页 
MC14051B, MC14052B,  
MC14053B  
Analog  
Multiplexers/Demultiplexers  
The MC14051B, MC14052B, and MC14053B analog multiplexers  
are digitally−controlled analog switches. The MC14051B effectively  
implements an SP8T solid state switch, the MC14052B a DP4T, and  
the MC14053B a Triple SPDT. All three devices feature low ON  
impedance and very low OFF leakage current. Control of analog  
signals up to the complete supply voltage range can be achieved.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
1
PDIP−16  
P SUFFIX  
CASE 648  
MC140xxBCP  
AWLYYWW  
Features  
• Triple Diode Protection on Control Inputs  
• Switch Function is Break Before Make  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
• Analog Voltage Range (V − V ) = 3.0 to 18 V  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
DD  
EE  
140xxB  
AWLYWW  
Note: V must be v V  
EE  
SS  
• Linearized Transfer Characteristics  
1
• Low−noise − 12 nV/√Cycle, f ≥ 1.0 kHz Typical  
• Pin−for−Pin Replacement for CD4051, CD4052, and CD4053  
• For 4PDT Switch, See MC14551B  
16  
14  
0xxB  
ALYW  
TSSOP−16  
DT SUFFIX  
CASE 948F  
• For Lower R , Use the HC4051, HC4052, or HC4053 High−Speed  
ON  
CMOS Devices  
1
• Pb−Free Packages are Available*  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
16  
1
Symbol  
Parameter  
Value  
Unit  
SOEIAJ−16  
F SUFFIX  
CASE 966  
MC140xxB  
AWLYWW  
V
DD  
DC Supply Voltage Range  
−0.5 to  
+18.0  
V
(Referenced to V , V ≥ V )  
EE  
EE  
SS  
V ,  
Input or Output Voltage Range  
(DC or Transient) (Referenced to V for  
−0.5 to V  
+ 0.5  
V
in  
DD  
V
out  
SS  
Control Inputs and V for Switch I/O)  
EE  
xx  
A
WL, L  
YY, Y  
= Specific Device Code  
= Assembly Location  
= Wafer Lot  
I
in  
Input Current (DC or Transient) per Control Pin  
Switch Through Current  
+10  
±25  
500  
mA  
mA  
mW  
I
SW  
= Year  
P
D
Power Dissipation per Package (Note 1)  
Ambient Temperature Range  
WW, W = Work Week  
T
A
−55 to +125 °C  
−65 to +150 °C  
T
stg  
Storage Temperature Range  
T
L
Lead Temperature (8−Second Soldering)  
260  
°C  
ORDERING INFORMATION  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From  
65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained to  
in  
out  
*For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either  
V , V or V ). Unused outputs must be left open.  
SS EE DD  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
February, 2005 − Rev. 6  
MC14051B/D  
 
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MC14053BFELG 替代型号

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