The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitally–controlled analog switches. The MC14051B effectively
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
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MARKING
DIAGRAMS
16
• Triple Diode Protection on Control Inputs
• Switch Function is Break Before Make
PDIP–16
P SUFFIX
CASE 648
MC140XXBCP
AWLYYWW
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Analog Voltage Range (V – V ) = 3.0 to 18 V
1
DD
EE
Note: V must be
V
EE
SS
16
1
• Linearized Transfer Characteristics
SOIC–16
D SUFFIX
CASE 751B
140XXB
AWLYWW
• Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical
• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053
• For 4PDT Switch, See MC14551B
16
• For Lower R , Use the HC4051, HC4052, or HC4053 High–Speed
ON
CMOS Devices
TSSOP–16
DT SUFFIX
CASE 948F
14
0XXB
ALYW
MAXIMUM RATINGS (Note 1.)
Symbol
Parameter
Value
Unit
1
V
DD
DC Supply Voltage (Referenced
–0.5 to +18.0
V
to V , V ≥ V )
EE
EE
SS
16
1
V , V
in out
Input or Output Voltage Range
(DC or Transient) (Referen–
–0.5 to V + 0.5
V
SOEIAJ–16
F SUFFIX
CASE 966
DD
MC140XXB
AWLYWW
ced to V for Control Inputs
SS
and V for Switch I/O)
EE
I
in
Input Current (DC or Transient)
per Control Pin
±10
mA
XX
A
= Specific Device Code
= Assembly Location
I
Switch Through Current
±25
mA
SW
P
D
Power Dissipation,
per Package (Note 2.)
500
mW
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
T
stg
T
Lead Temperature
L
ORDERING INFORMATION
(8–Second Soldering)
Seedetailedorderingandshippinginformationinthepackage
dimensions section on page 12 of this data sheet.
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V , V or V ). Unused outputs must be left open.
SS
EE
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14051B/D