The MC14029B Binary/Decade up/down counter is constructed
with MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. The counter consists of type D flip–flop
stages with a gating structure to provide toggle flip–flop capability.
The counter can be used in either Binary or BCD operation. This
complementary MOS counter finds primary use in up/down and
difference counting and frequency synthesizer applications where low
power dissipation and/or high noise immunity is desired. It is also
useful in A/D and D/A conversion and for magnitude and sign
generation.
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC14029BCP
AWLYYWW
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Internally Synchronous for High Speed
• Logic Edge–Clocked Design — Count Occurs on Positive Going
Edge of Clock
1
16
SOIC–16
D SUFFIX
CASE 751B
14029B
AWLYWW
• Asynchronous Preset Enable Operation
1
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin for Pin Replacement for CD4029B
16
SOEIAJ–16
F SUFFIX
CASE 966
MC14029B
AWLYWW
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
1
SS
Symbol
Parameter
Value
Unit
V
A
= Assembly Location
V
DD
DC Supply Voltage Range
–0.5 to +18.0
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
ORDERING INFORMATION
P
D
Power Dissipation,
500
mW
per Package (Note 3.)
Device
Package
PDIP–16
SOIC–16
Shipping
T
A
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
MC14029BCP
MC14029BD
2000/Box
2400/Box
T
stg
T
L
Lead Temperature
(8–Second Soldering)
MC14029BDR2
SOIC–16 2500/Tape & Reel
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
MC14029BF
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
MC14029BFEL
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14029B/D