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MC14023UBCP

更新时间： 2024-11-29 22:11:03

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		栅
页数	文件大小	规格书
7页	324K
描述
UB-Suffix Series COMS Gates

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数据手册

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MC14023UBCP 数据手册

SEMICONDUCTOR TECHNICAL DATA

The UB Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure (Complemen-

tary MOS). Their primary use is where low power dissipation and/or high

noise immunity is desired. The UB set of CMOS gates are inverting

non–buffered functions.

•

Supply Voltage Range = 3.0 Vdc to 18 Vdc

Linear and Oscillator Applications

Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

Double Diode Protection on All Inputs

•

Pin–for–Pin Replacements for Corresponding CD4000 Series UB Suffix

Devices

LOGIC DIAGRAMS

MC14001UB

Quad 2–Input

NOR Gate

MC14002UB

Dual 4–Input

NOR Gate

MC14011UB

Quad 2–Input

NAND Gate

L SUFFIX

CERAMIC

CASE 632

P SUFFIX

PLASTIC

CASE 646

NC = 6, 8

D SUFFIX

SOIC

CASE 751A

MC14012UB

Dual 4–Input

NAND Gate

MC14023UB

Triple 3–Input

NAND Gate

MC14025UB

Triple 3–Input

NOR Gate

ORDERING INFORMATION

MC14XXXUBCP

MC14XXXUBCL

MC14XXXUBD

Plastic

Ceramic

SOIC

= – 55° to 125°C for all packages.

This device contains protection circuitry to

guard against damage due to high static

voltages or electric fields. However, pre-

cautions must be taken to avoid applications of

any voltage higher than maximum rated volt-

agesto this high–impedance circuit. For proper

NC = 6, 8

= PIN 14

= PIN 7

operation, V and V

should be constrained

FOR ALL DEVICES

in out

to the range V

(V or V

)

SS in out

Unused inputs must always be tied to an

appropriatelogic voltage level (e.g., either V

or V ). Unused outputs must be left open.

REV 3

1/94

Motorola, Inc. 1995

MC14001UB

MOTOROLA CMOS LOGIC DATA

12 3 4 5 6 7

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