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MC14012BFELG

更新时间： 2024-09-25 04:59:35
品牌 Logo 应用领域
安森美 - ONSEMI 栅
页数 文件大小 规格书
9页 150K
描述
B−Suffix Series CMOS Gates

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MC14012BFELG 数据手册

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MC14012B  
B−Suffix Series CMOS Gates  
The B Series logic gates are constructed with P−Channel and  
N−Channel enhancement mode devices in a single monolithic  
structure (Complementary MOS). Their primary use is where low  
power dissipation and/or high noise immunity is desired.  
http://onsemi.com  
Features  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
• All Outputs Buffered  
MARKING  
DIAGRAMS  
• Capable of Driving Two Low−Power TTL Loads or One Low−Power  
Schottky TTL Load Over the Rated Temperature Range  
• Double Diode Protection on All Inputs  
• Pin−for−Pin Replacements for Corresponding CD4000 Series B  
Suffix Devices  
14  
1
PDIP−14  
P SUFFIX  
CASE 646  
MC14012BCP  
AWLYYWWG  
• Pb−Free Packages are Available  
14  
SOIC−14  
D SUFFIX  
CASE 751A  
14012BG  
AWLYWW  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
−0.5 to +18.0  
Unit  
V
1
V
DC Supply Voltage Range  
DD  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
14  
SOEIAJ−14  
F SUFFIX  
CASE 965  
MC14012B  
ALYWG  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
P
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
1
T
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
A
T
stg  
T
Lead Temperature  
WW, W = Work Week  
L
(8−Second Soldering)  
G
= Pb−Free Package  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating:  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
October, 2006 − Rev. 7  
MC14012B/D  
 
1234567...9

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MC14012BFELG 替代型号

型号 品牌 替代类型 描述 数据表
CD4012BNSRG4 TI

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