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MC14012B PDF预览

MC14012B

更新时间: 2024-11-03 22:58:11
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
8页 181K
描述
B-Suffix Series CMOS Gates

MC14012B 数据手册

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The B Series logic gates are constructed with P and N channel  
enhancement mode devices in a single monolithic structure  
(Complementary MOS). Their primary use is where low power  
dissipation and/or high noise immunity is desired.  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
All Outputs Buffered  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range.  
Double Diode Protection on All Inputs  
http://onsemi.com  
MARKING  
DIAGRAMS  
14  
PDIP–14  
P SUFFIX  
CASE 646  
Pin–for–Pin Replacements for Corresponding CD4000 Series B  
MC14012BCP  
AWLYYWW  
Suffix Devices  
1
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)  
SS  
14  
Symbol  
Parameter  
Value  
Unit  
V
SOIC–14  
D SUFFIX  
CASE 751A  
14012B  
AWLYWW  
V
DD  
DC Supply Voltage Range  
0.5 to +18.0  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
0.5 to V + 0.5  
V
DD  
1
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
14  
SOEIAJ–14  
F SUFFIX  
CASE 965  
P
Power Dissipation,  
per Package (Note 3.)  
500  
mW  
D
MC14012B  
AWLYWW  
T
A
Ambient Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
1
T
stg  
T
Lead Temperature  
(8–Second Soldering)  
L
A
= Assembly Location  
WL or L = Wafer Lot  
YY or Y = Year  
2. Maximum Ratings are those values beyond which damage to the device  
may occur.  
WW or W = Work Week  
3. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
ORDERING INFORMATION  
Device  
Package  
PDIP–14  
SOIC–14  
Shipping  
high–impedancecircuit. For proper operation, V and V should be constrained  
in  
out  
MC14012BCP  
MC14012BD  
2000/Box  
55/Rail  
to the range V  
(V or V  
)
V
DD  
.
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
MC14012BDR2  
MC14012BF  
SOIC–14 2500/Tape & Reel  
SOEIAJ–14  
SOEIAJ–14  
See Note 1.  
See Note 1.  
MC14012BFEL  
1. For ordering information on the EIAJ version of  
the SOIC packages, please contact your local  
ON Semiconductor representative.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
April, 2000 – Rev. 3  
MC14012B/D  

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