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MC14011BDCBS PDF预览

MC14011BDCBS

更新时间: 2024-02-14 07:06:56
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA
页数 文件大小 规格书
7页 324K
描述
NAND Gate, CMOS, CDIP14

MC14011BDCBS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-XDIP-T14
JESD-609代码:e0逻辑集成电路类型:NAND GATE
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5/15 V认证状态:Not Qualified
施密特触发器:NO筛选级别:MIL-STD-883 Class B (Modified)
子类别:Gates表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

MC14011BDCBS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The UB Series logic gates are constructed with P and N channel  
enhancement mode devices in a single monolithic structure (Complemen-  
tary MOS). Their primary use is where low power dissipation and/or high  
noise immunity is desired. The UB set of CMOS gates are inverting  
non–buffered functions.  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Linear and Oscillator Applications  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
Double Diode Protection on All Inputs  
Pin–for–Pin Replacements for Corresponding CD4000 Series UB Suffix  
Devices  
LOGIC DIAGRAMS  
MC14001UB  
Quad 2–Input  
NOR Gate  
MC14002UB  
Dual 4–Input  
NOR Gate  
MC14011UB  
Quad 2–Input  
NAND Gate  
L SUFFIX  
CERAMIC  
CASE 632  
2
1
1
2
3
3
3
4
2
5
1
5
6
4
4
6
8
5
9
10  
11  
12  
8
10  
11  
10  
11  
P SUFFIX  
PLASTIC  
CASE 646  
9
9
12  
13  
12  
13  
13  
NC = 6, 8  
D SUFFIX  
SOIC  
CASE 751A  
MC14012UB  
Dual 4–Input  
NAND Gate  
MC14023UB  
Triple 3–Input  
NAND Gate  
MC14025UB  
Triple 3–Input  
NOR Gate  
1
1
2
ORDERING INFORMATION  
2
3
9
2
9
MC14XXXUBCP  
MC14XXXUBCL  
MC14XXXUBD  
Plastic  
Ceramic  
SOIC  
1
8
3
8
3
4
5
9
4
6
4
5
11  
6
T
= – 55° to 125°C for all packages.  
A
5
11  
10  
11  
12  
13  
12  
13  
10  
12  
13  
10  
This device contains protection circuitry to  
guard against damage due to high static  
voltages or electric fields. However, pre-  
cautions must be taken to avoid applications of  
any voltage higher than maximum rated volt-  
agesto this high–impedance circuit. For proper  
NC = 6, 8  
V
V
= PIN 14  
= PIN 7  
DD  
SS  
operation, V and V  
should be constrained  
FOR ALL DEVICES  
in out  
to the range V  
(V or V  
)
V
DD  
.
SS in out  
Unused inputs must always be tied to an  
appropriatelogic voltage level (e.g., either V  
SS  
or V ). Unused outputs must be left open.  
DD  
REV 3  
1/94  
Motorola, Inc. 1995  

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