MC10H210
Dual 3−Input 3−Output OR
Gate
Description
The MC10H210 is designed to drive up to six transmission lines
simultaneously. The multiple outputs of this device also allow the wire
ORing of several levels of gating for minimization of gate and package
count.
The ability to control three parallel lines with minimum propagation
delay from a single point makes the MC10H210 particularly useful in
clock distribution applications where minimum clock skew is desired.
http://onsemi.com
MARKING DIAGRAMS*
16
Features
MC10H210L
AWLYYWW
• Propagation Delay Average, 1.0 ns Typical
• Power Dissipation, 160 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
1
CDIP−16
L SUFFIX
CASE 620A
• Voltage Compensated
• MECL 10K™ Compatible
16
1
• Pb−Free Packages are Available*
MC10H210P
AWLYYWWG
16
LOGIC DIAGRAM
1
5
6
7
2
3
4
PDIP−16
P SUFFIX
CASE 648
9
10
11
12
13
14
10H210
ALYWG
V
V
V
= PINS 1, 15
= PIN 16
CC1
CC2
SOEIAJ−16
CASE 966
= PIN 8
EE
DIP
1 20
PIN ASSIGNMENT
V
A
V
V
B
B
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
CC2
CC1
OUT
OUT
OUT
10H210G
AWLYYWW
20
1
OUT
OUT
OUT
PLLC−20
FN SUFFIX
CASE 775
A
A
A
IN
A
= Assembly Location
= Year
WL, L = Wafer Lot
YY, Y
WW, W = Work Week
G
A
B
B
B
IN
IN
IN
IN
A
IN
= Pb−Free Package
V
EE
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
*For additional marking information, refer to
Application Note AND8002/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
February, 2006 − Rev. 7
MC10H210/D