5秒后页面跳转
MC10H210FN PDF预览

MC10H210FN

更新时间: 2024-11-04 04:59:39
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
6页 150K
描述
Dual 3−Input 3−Output OR Gate

MC10H210FN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:7.82系列:10H
JESD-30 代码:S-PQCC-J20JESD-609代码:e0
长度:8.965 mm逻辑集成电路类型:OR GATE
湿度敏感等级:1功能数量:2
输入次数:3端子数量:20
最高工作温度:75 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:RAIL
峰值回流温度(摄氏度):240Prop。Delay @ Nom-Sup:1.7 ns
传播延迟(tpd):1.55 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:4.57 mm
子类别:Gates表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:8.965 mm

MC10H210FN 数据手册

 浏览型号MC10H210FN的Datasheet PDF文件第2页浏览型号MC10H210FN的Datasheet PDF文件第3页浏览型号MC10H210FN的Datasheet PDF文件第4页浏览型号MC10H210FN的Datasheet PDF文件第5页浏览型号MC10H210FN的Datasheet PDF文件第6页 
MC10H210  
Dual 3−Input 3−Output OR  
Gate  
Description  
The MC10H210 is designed to drive up to six transmission lines  
simultaneously. The multiple outputs of this device also allow the wire  
ORing of several levels of gating for minimization of gate and package  
count.  
The ability to control three parallel lines with minimum propagation  
delay from a single point makes the MC10H210 particularly useful in  
clock distribution applications where minimum clock skew is desired.  
http://onsemi.com  
MARKING DIAGRAMS*  
16  
Features  
MC10H210L  
AWLYYWW  
Propagation Delay Average, 1.0 ns Typical  
Power Dissipation, 160 mW Typical  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
1
CDIP16  
L SUFFIX  
CASE 620A  
Voltage Compensated  
MECL 10KCompatible  
16  
1
PbFree Packages are Available*  
MC10H210P  
AWLYYWWG  
16  
LOGIC DIAGRAM  
1
5
6
7
2
3
4
PDIP16  
P SUFFIX  
CASE 648  
9
10  
11  
12  
13  
14  
10H210  
ALYWG  
V
V
V
= PINS 1, 15  
= PIN 16  
CC1  
CC2  
SOEIAJ16  
CASE 966  
= PIN 8  
EE  
DIP  
1 20  
PIN ASSIGNMENT  
V
A
V
V
B
B
B
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
CC2  
CC1  
OUT  
OUT  
OUT  
10H210G  
AWLYYWW  
20  
1
OUT  
OUT  
OUT  
PLLC20  
FN SUFFIX  
CASE 775  
A
A
A
IN  
A
= Assembly Location  
= Year  
WL, L = Wafer Lot  
YY, Y  
WW, W = Work Week  
G
A
B
B
B
IN  
IN  
IN  
IN  
A
IN  
= PbFree Package  
V
EE  
Pin assignment is for DualinLine Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
*For additional marking information, refer to  
Application Note AND8002/D.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
February, 2006 Rev. 7  
MC10H210/D  

与MC10H210FN相关器件

型号 品牌 获取价格 描述 数据表
MC10H210FNG ONSEMI

获取价格

Dual 3−Input 3−Output OR Gate
MC10H210FNR2 ONSEMI

获取价格

Dual 3−Input 3−Output OR Gate
MC10H210FNR2G ONSEMI

获取价格

Dual 3−Input 3−Output OR Gate
MC10H210L ONSEMI

获取价格

Dual 3−Input 3−Output OR Gate
MC10H210L MOTOROLA

获取价格

Dual 3-Input 3-Output OR Gate
MC10H210LD MOTOROLA

获取价格

OR Gate, ECL, CDIP16
MC10H210LDS MOTOROLA

获取价格

OR Gate, ECL, CDIP16
MC10H210LS MOTOROLA

获取价格

IC,LOGIC GATE,DUAL 3-INPUT OR,ECL,DIP,16PIN,CERAMIC
MC10H210M ONSEMI

获取价格

Dual 3−Input 3−Output OR Gate
MC10H210MEL ONSEMI

获取价格

Dual 3−Input 3−Output OR Gate