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MC10H209M

更新时间： 2024-11-04 04:20:23

品牌	Logo	应用领域
安森美 - ONSEMI		栅
页数	文件大小	规格书
6页	150K
描述
Dual 4−5−Input OR/NOR Gate

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中文翻译

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数据手册

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MC10H209M 数据手册

MC10H209

Dual 4−5−Input OR/NOR

Gate

Description

The MC10H209 is a Dual 4−5−input OR/NOR gate. This MECL

part is a functional/pinout duplication of the MECL III part MC1688.

http://onsemi.com

MARKING DIAGRAMS*

Features

• Propagation Delay Average, 0.75 ns Typical

• Power Dissipation 125 mW Typical

• Improved Noise Margin 150 mV (Over Operating Voltage and

MC10H209L

AWLYYWW

Temperature Range)

• Voltage Compensated

• MECL 10K™ Compatible

CDIP−16

L SUFFIX

CASE 620A

• Pb−Free Packages are Available*

LOGIC DIAGRAM

MC10H209P

AWLYYWW

PDIP−16

P SUFFIX

CASE 648

10H209

ALYWG

= PIN 1

= PIN 16

CC1

CC2

= PIN 8

SOEIAJ−16

CASE 966

DIP

PIN ASSIGNMENT

1 20

CC1

CC2

10H209G

AWLYYWW

OUT

PLLC−20

FN SUFFIX

CASE 775

= Assembly Location

= Year

WL, L = Wafer Lot

YY, Y

WW, W = Work Week

= Pb−Free Package

Pin assignment is for Dual−in−Line Package.

For PLCC pin assignment, see the Pin Conversion Tables on page 18

of the ON Semiconductor MECL Data Book (DL122/D).

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

February, 2006 − Rev. 7

MC10H209/D

12 3 4 5 6

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MC10H209PD	MOTOROLA	获取价格	Gate, ECL, PDIP16
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