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MC10H175LD PDF预览

MC10H175LD

更新时间: 2024-11-04 13:11:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
4页 98K
描述
D Latch, 1-Func, 5-Bit, ECL, CDIP16

MC10H175LD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
JESD-30 代码:R-XDIP-T16JESD-609代码:e0
逻辑集成电路类型:D LATCH位数:5
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE子类别:FF/Latches
表面贴装:NO技术:ECL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC10H175LD 数据手册

 浏览型号MC10H175LD的Datasheet PDF文件第2页浏览型号MC10H175LD的Datasheet PDF文件第3页浏览型号MC10H175LD的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10H175 is a quint D type latch with common reset and clock lines.  
This MECL 10KH part is a functional/pinout duplication of the standard MECL  
10K family part, with 100% improvement in propagation delay and no increase  
in power–supply current.  
Propagation Delay, 1.2 ns Typical  
Power Dissipation, 400 mW Typical  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
Voltage Compensated  
MECL 10K–Compatible  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
MAXIMUM RATINGS  
Characteristic  
Symbol  
Rating  
Unit  
Vdc  
Vdc  
mA  
FN SUFFIX  
PLCC  
CASE 775–02  
Power Supply (V  
= 0)  
V
EE  
–8.0 to 0  
CC  
Input Voltage (V  
= 0)  
V
I
0 to V  
50  
CC  
EE  
Output CurrentContinuous  
— Surge  
I
out  
100  
Operating Temperature Range  
T
A
0 to +75  
°C  
TRUTH TABLE  
Storage Temperature RangePlastic  
— Ceramic  
T
stg  
–55 to +150  
–55 to +165  
°C  
°C  
D
C0  
C1  
Reset  
Q
n+1  
L
H
Qn  
Qn  
L
L
L
H
X
H
X
L
L
X
H
X
H
X
X
L
L
H
H
L
H
X
X
X
X
ELECTRICAL CHARACTERISTICS (V  
0°  
= –5.2 V ±5%) (See Note)  
EE  
25°  
75°  
Characteristic  
Symbol Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Power Supply Current  
I
E
107  
97  
107  
mA  
L
Input Current High  
Pins 5,6,7,9,10,12,13  
Pin 11  
I
µA  
inH  
565  
335  
660  
335  
660  
1120  
Input Current Low  
High Output Voltage  
Low Output Voltage  
High Input Voltage  
Low Input Voltage  
I
0.5  
0.5  
0.3  
µA  
inL  
DIP  
PIN ASSIGNMENT  
V
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc  
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc  
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc  
OH  
V
OL  
V
IH  
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
V
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45  
Vdc  
IL  
Q2  
Q3  
Q4  
D4  
C0  
C1  
Q1  
Q0  
D2  
D1  
AC PARAMETERS  
Propagation Delay  
Data  
Clock  
Reset  
t
pd  
ns  
0.6  
0.7  
1.0  
1.6  
1.9  
2.2  
0.6  
0.7  
1.0  
1.6  
2.0  
2.3  
0.6  
0.8  
1.0  
1.7  
2.1  
2.4  
Set–up Time  
Hold Time  
Rise Time  
Fall Time  
NOTE:  
t
1.5  
0.8  
0.5  
0.5  
1.5  
0.8  
0.5  
0.5  
1.5  
0.8  
0.5  
0.5  
ns  
ns  
ns  
ns  
set  
RESET  
D0  
t
hold  
t
r
1.8  
1.8  
1.9  
1.9  
2.0  
2.0  
t
f
D3  
V
EE  
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test  
table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a  
printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are  
terminated through a 50–ohm resistor to –2.0 volts.  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
3/93  
Motorola, Inc. 1996  
REV 5  

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