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MC10H172P PDF预览

MC10H172P

更新时间: 2024-09-23 05:10:23
品牌 Logo 应用领域
安森美 - ONSEMI 解码器逻辑集成电路光电二极管驱动
页数 文件大小 规格书
5页 144K
描述
Dual Binary to 1−4−Decoder (High)

MC10H172P 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:7.8系列:10H
输入调节:STANDARDJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.175 mm
逻辑集成电路类型:OTHER DECODER/DRIVER功能数量:2
端子数量:16最高工作温度:75 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:RAIL峰值回流温度(摄氏度):235
最大电源电流(ICC):85 mAProp。Delay @ Nom-Sup:2.8 ns
传播延迟(tpd):2.1 ns认证状态:Not Qualified
座面最大高度:4.44 mm子类别:Decoder/Drivers
表面贴装:NO技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn80Pb20)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MC10H172P 数据手册

 浏览型号MC10H172P的Datasheet PDF文件第2页浏览型号MC10H172P的Datasheet PDF文件第3页浏览型号MC10H172P的Datasheet PDF文件第4页浏览型号MC10H172P的Datasheet PDF文件第5页 
MC10H172  
Dual Binary to 1−4−Decoder  
(High)  
Description  
The MC10H172 is a binary coded 2 line to dual 4 line decoder with  
selected outputs high. With either E0 or E1 low, the corresponding  
selected 4 outputs are low. The common enable E, when high, forces  
all outputs low.  
http://onsemi.com  
MARKING DIAGRAMS*  
Features  
Propagation Delay, 2 ns Typical  
Power Dissipation 325 mW Typical (same as MECL 10K)  
Improved Noise Margin 150 mV (over operating voltage and  
temperature range)  
16  
MC10H172L  
AWLYYWW  
Voltage Compensated  
1
CDIP16  
L SUFFIX  
CASE 620A  
MECL 10K Compatible  
PbFree Packages are Available*  
LOGIC DIAGRAM  
E0 14  
10 Q0 3  
16  
1
11 Q0 2  
12 Q0 1  
MC10H172P  
AWLYYWWG  
16  
V
V
V
= PIN 1  
= PIN 16  
CC1  
CC2  
1
A 9  
B 7  
13 Q0 0  
3 Q1 3  
4 Q1 2  
5 Q1 1  
6 Q1 0  
= PIN 8  
EE  
PDIP16  
P SUFFIX  
CASE 648  
E 15  
E1 2  
1 20  
DIP  
10H172G  
AWLYYWW  
20  
1
PIN ASSIGNMENT  
PLLC20  
FN SUFFIX  
CASE 775  
V
V
E
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
CC2  
E1  
Q13  
Q12  
Q11  
Q10  
B
E0  
A
= Assembly Location  
= Year  
Q00  
Q01  
Q02  
Q03  
A
WL, L = Wafer Lot  
YY, Y  
WW, W = Work Week  
G
= PbFree Package  
V
EE  
*For additional marking information, refer to  
Application Note AND8002/D.  
Pin assignment is for DualinLine Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
February, 2006 Rev. 7  
MC10H172/D  

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