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MC10H117P PDF预览

MC10H117P

更新时间: 2024-11-26 05:10:23
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
6页 152K
描述
Dual 2−Wide 2−3−Input OR−AND/OR−AND Gate

MC10H117P 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:PLASTIC, DIP-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:7.76其他特性:COMMON INPUT
系列:10HJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.175 mm
逻辑集成电路类型:OR-AND/OR-AND-INVERT GATE功能数量:2
输入次数:5端子数量:16
最高工作温度:75 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:RAIL
峰值回流温度(摄氏度):240Prop。Delay @ Nom-Sup:1.5 ns
传播延迟(tpd):1.35 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:4.44 mm
子类别:Gates表面贴装:NO
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.62 mm
Base Number Matches:1

MC10H117P 数据手册

 浏览型号MC10H117P的Datasheet PDF文件第2页浏览型号MC10H117P的Datasheet PDF文件第3页浏览型号MC10H117P的Datasheet PDF文件第4页浏览型号MC10H117P的Datasheet PDF文件第5页浏览型号MC10H117P的Datasheet PDF文件第6页 
MC10H117  
Dual 2−Wide 2−3−Input  
OR−AND/OR−AND Gate  
Description  
The MC10H117 dual 2wide 23input ORAND/  
ORANDInvertgate is a general purpose logic element designed for  
use in data control, such as digital multiplexing or data distribution.  
Pin 9 is common to both gates. This MECL 10Hpart is a  
functional/pinout duplication of the standard MECL 10Kfamily  
part, with 100% improvement in propagation delay, and no increase in  
powersupply current.  
http://onsemi.com  
MARKING DIAGRAMS*  
16  
MC10H117L  
AWLYYWW  
Features  
Propagation Delay, 1.0 ns Typical  
Power Dissipation 100 mW/Gate Typical (same as MECL 10K)  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
1
CDIP16  
L SUFFIX  
CASE 620A  
Voltage Compensated  
MECL 10K Compatible  
16  
1
PbFree Packages are Available*  
MC10H117P  
AWLYYWWG  
16  
1
PDIP16  
P SUFFIX  
CASE 648  
10H117  
ALYWG  
SOEIAJ16  
CASE 966  
1 20  
10H117G  
AWLYYWW  
20  
1
PLLC20  
FN SUFFIX  
CASE 775  
A
= Assembly Location  
= Year  
WL, L = Wafer Lot  
YY, Y  
WW, W = Work Week  
G
= PbFree Package  
*For additional marking information, refer to  
Application Note AND8002/D.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
February, 2006 Rev. 7  
MC10H117/D  

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