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MC10H117MELG PDF预览

MC10H117MELG

更新时间: 2024-09-16 05:10:23
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 152K
描述
Dual 2−Wide 2−3−Input OR−AND/OR−AND Gate

MC10H117MELG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:LEAD FREE, EIAJ, SO-16
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.65
Is Samacsys:N系列:10H
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:10.2 mm逻辑集成电路类型:OR-AND/OR-AND-INVERT GATE
功能数量:2输入次数:5
端子数量:16最高工作温度:75 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
Prop。Delay @ Nom-Sup:1.5 ns传播延迟(tpd):1.35 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.05 mm子类别:Gates
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:5.275 mmBase Number Matches:1

MC10H117MELG 数据手册

 浏览型号MC10H117MELG的Datasheet PDF文件第2页浏览型号MC10H117MELG的Datasheet PDF文件第3页浏览型号MC10H117MELG的Datasheet PDF文件第4页浏览型号MC10H117MELG的Datasheet PDF文件第5页浏览型号MC10H117MELG的Datasheet PDF文件第6页 
MC10H117  
Dual 2−Wide 2−3−Input  
OR−AND/OR−AND Gate  
Description  
The MC10H117 dual 2wide 23input ORAND/  
ORANDInvertgate is a general purpose logic element designed for  
use in data control, such as digital multiplexing or data distribution.  
Pin 9 is common to both gates. This MECL 10Hpart is a  
functional/pinout duplication of the standard MECL 10Kfamily  
part, with 100% improvement in propagation delay, and no increase in  
powersupply current.  
http://onsemi.com  
MARKING DIAGRAMS*  
16  
MC10H117L  
AWLYYWW  
Features  
Propagation Delay, 1.0 ns Typical  
Power Dissipation 100 mW/Gate Typical (same as MECL 10K)  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
1
CDIP16  
L SUFFIX  
CASE 620A  
Voltage Compensated  
MECL 10K Compatible  
16  
1
PbFree Packages are Available*  
MC10H117P  
AWLYYWWG  
16  
1
PDIP16  
P SUFFIX  
CASE 648  
10H117  
ALYWG  
SOEIAJ16  
CASE 966  
1 20  
10H117G  
AWLYYWW  
20  
1
PLLC20  
FN SUFFIX  
CASE 775  
A
= Assembly Location  
= Year  
WL, L = Wafer Lot  
YY, Y  
WW, W = Work Week  
G
= PbFree Package  
*For additional marking information, refer to  
Application Note AND8002/D.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
February, 2006 Rev. 7  
MC10H117/D  

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