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MC10H117L PDF预览

MC10H117L

更新时间： 2024-11-25 22:51:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 栅极触发器逻辑集成电路
页数 文件大小 规格书
3页 101K
描述
Dual 2-Wide 2-3-input OR-AND/OR-AND Gate

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中文翻译

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MC10H117L 技术参数

生命周期：Transferred零件包装代码：DIP
包装说明：DIP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.48Is Samacsys：N
其他特性：COMMON INPUT系列：10H
JESD-30 代码：R-GDIP-T16JESD-609代码：e0
长度：19.495 mm逻辑集成电路类型：OR-AND/OR-AND-INVERT GATE
功能数量：2输入次数：5
端子数量：16最高工作温度：75 °C
最低工作温度：输出特性：OPEN-EMITTER
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
最大电源电流（ICC）：29 mA传播延迟（tpd）：1.5 ns
认证状态：Not Qualified座面最大高度：5.08 mm
表面贴装：NO技术：ECL
温度等级：COMMERCIAL EXTENDED端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

MC10H117L 数据手册

 浏览型号MC10H117L的Datasheet PDF文件第2页浏览型号MC10H117L的Datasheet PDF文件第3页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10H117 dual 2–wide 2–3–input OR–AND/OR–AND–Invert gate is a  
general purpose logic element designed for use in data control, such as digital  
multiplexing or data distribution. Pin 9 is common to both gates. This MECL 10H  
part is a functional/pinout duplication of the standard MECL 10K family part,  
with 100% improvement in propagation delay, and no increase in power–supply  
current.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
•
•
•
Propagation Delay, 1.0 ns Typical  
Power Dissipation 100 mW/Gate Typical (same as MECL 10K)  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
FN SUFFIX  
PLCC  
CASE 775–02  
•
•
Voltage Compensated  
MECL 10K–Compatible  
LOGIC DIAGRAM  
MAXIMUM RATINGS  
Characteristic  
Symbol  
Rating  
Unit  
Vdc  
Vdc  
mA  
4
5
Power Supply (V  
= 0)  
V
EE  
–8.0 to 0  
CC  
3
2
Input Voltage (V  
= 0)  
V
I
0 to V  
CC  
EE  
6
7
Output Current— Continuous  
— Surge  
I
out  
50  
100  
Operating Temperature Range  
T
A
0 to +75  
°C  
9
Storage Temperature Range— Plastic  
— Ceramic  
T
–55 to +150  
–55 to +165  
°C  
°C  
stg  
10  
11  
ELECTRICAL CHARACTERISTICS (V  
0°  
= –5.2 V ±5%) (See Note)  
14  
15  
EE  
25°  
75°  
12  
13  
Characteristic  
Symbol Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Power Supply Current  
I
—
29  
—
26  
—
29  
mA  
E
V
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
Input Current High  
Pins 4, 5, 12, 13  
Pins 6, 7, 10, 11  
Pin 9  
I
µA  
inH  
—
—
—
465  
545  
710  
—
—
—
275  
320  
415  
—
—
—
275  
320  
415  
DIP  
Input Current Low  
High Output Voltage  
Low Output Voltage  
High Input Voltage  
Low Input Voltage  
I
0.5  
—
0.5  
—
0.3  
—
µA  
inL  
PIN ASSIGNMENT  
V
OH  
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc  
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc  
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc  
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc  
V
OL  
V
A
V
B
B
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
CC2  
OUT  
OUT  
V
IH  
OUT  
OUT  
V
IL  
A
AC PARAMETERS  
Propagation Delay  
Rise Time  
B1  
A1  
A1  
A2  
A2  
V
t
pd  
0.45  
0.5  
1.35  
1.5  
0.45  
0.5  
1.35  
1.6  
0.5  
0.5  
0.5  
1.5  
1.7  
1.7  
ns  
ns  
ns  
IN  
IN  
IN  
IN  
IN  
IN  
t
r
B1  
Fall Time  
t
0.5  
1.5  
0.5  
1.6  
f
B2  
B2  
A2  
IN  
NOTE:  
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,  
afterthermalequilibriumhasbeenestablished.Thecircuitisinatestsocketormountedonaprintedcircuit  
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through  
a 50–ohm resistor to –2.0 volts.  
IN  
B2  
IN, IN  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
3/93  
Motorola, Inc. 1996  
REV 5  
123

中文翻译

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