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MC10H117

更新时间： 2024-09-15 22:58:11
品牌 Logo 应用领域
安森美 - ONSEMI 栅
页数 文件大小 规格书
3页 101K
描述
Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate

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MC10H117 数据手册

 浏览型号MC10H117的Datasheet PDF文件第2页浏览型号MC10H117的Datasheet PDF文件第3页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10H117 dual 2–wide 2–3–input OR–AND/OR–AND–Invert gate is a  
general purpose logic element designed for use in data control, such as digital  
multiplexing or data distribution. Pin 9 is common to both gates. This MECL 10H  
part is a functional/pinout duplication of the standard MECL 10K family part,  
with 100% improvement in propagation delay, and no increase in power–supply  
current.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
•
•
•
Propagation Delay, 1.0 ns Typical  
Power Dissipation 100 mW/Gate Typical (same as MECL 10K)  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
FN SUFFIX  
PLCC  
CASE 775–02  
•
•
Voltage Compensated  
MECL 10K–Compatible  
LOGIC DIAGRAM  
MAXIMUM RATINGS  
Characteristic  
Symbol  
Rating  
Unit  
Vdc  
Vdc  
mA  
4
5
Power Supply (V  
= 0)  
V
EE  
–8.0 to 0  
CC  
3
2
Input Voltage (V  
= 0)  
V
I
0 to V  
CC  
EE  
6
7
Output Current— Continuous  
— Surge  
I
out  
50  
100  
Operating Temperature Range  
T
A
0 to +75  
°C  
9
Storage Temperature Range— Plastic  
— Ceramic  
T
–55 to +150  
–55 to +165  
°C  
°C  
stg  
10  
11  
ELECTRICAL CHARACTERISTICS (V  
0°  
= –5.2 V ±5%) (See Note)  
14  
15  
EE  
25°  
75°  
12  
13  
Characteristic  
Symbol Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Power Supply Current  
I
—
29  
—
26  
—
29  
mA  
E
V
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
Input Current High  
Pins 4, 5, 12, 13  
Pins 6, 7, 10, 11  
Pin 9  
I
µA  
inH  
—
—
—
465  
545  
710  
—
—
—
275  
320  
415  
—
—
—
275  
320  
415  
DIP  
Input Current Low  
High Output Voltage  
Low Output Voltage  
High Input Voltage  
Low Input Voltage  
I
0.5  
—
0.5  
—
0.3  
—
µA  
inL  
PIN ASSIGNMENT  
V
OH  
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc  
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc  
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc  
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc  
V
OL  
V
A
V
B
B
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
CC2  
OUT  
OUT  
V
IH  
OUT  
OUT  
V
IL  
A
AC PARAMETERS  
Propagation Delay  
Rise Time  
B1  
A1  
A1  
A2  
A2  
V
t
pd  
0.45  
0.5  
1.35  
1.5  
0.45  
0.5  
1.35  
1.6  
0.5  
0.5  
0.5  
1.5  
1.7  
1.7  
ns  
ns  
ns  
IN  
IN  
IN  
IN  
IN  
IN  
t
r
B1  
Fall Time  
t
0.5  
1.5  
0.5  
1.6  
f
B2  
B2  
A2  
IN  
NOTE:  
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,  
afterthermalequilibriumhasbeenestablished.Thecircuitisinatestsocketormountedonaprintedcircuit  
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through  
a 50–ohm resistor to –2.0 volts.  
IN  
B2  
IN, IN  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
3/93  
Motorola, Inc. 1996  
REV 5  
123

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