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MC10H105

更新时间： 2024-02-21 17:16:22
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安森美 - ONSEMI 栅
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3页 98K
描述
Triple 2-3-2-Input OR/NOR Gate

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MC10H105 数据手册

 浏览型号MC10H105的Datasheet PDF文件第2页浏览型号MC10H105的Datasheet PDF文件第3页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10H105 is a triple 2–3–2–input OR/NOR gate. This MECL 10H part  
is a functional/pinout duplication of the standard MECL 10K family part, with  
100% improvement in propagation delay, and no increases in power–supply  
current.  
•
•
•
Propagation Delay, 1.0 ns Typical  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
Power Dissipation 25 mW/Gate (same as MECL 10K)  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
•
•
Voltage Compensated  
MECL 10K–Compatible  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
FN SUFFIX  
PLCC  
CASE 775–02  
MAXIMUM RATINGS  
Characteristic  
Symbol  
Rating  
Unit  
Vdc  
Vdc  
mA  
Power Supply (V  
= 0)  
V
EE  
–8.0 to 0  
CC  
LOGIC DIAGRAM  
Input Voltage (V  
= 0)  
V
I
0 to V  
CC  
EE  
4
5
3
2
Output Current— Continuous  
— Surge  
I
out  
50  
100  
Operating Temperature Range  
T
A
0 to +75  
°C  
9
10  
11  
6
7
Storage Temperature Range— Plastic  
— Ceramic  
T
stg  
–55 to +150  
–55 to +165  
°C  
°C  
ELECTRICAL CHARACTERISTICS (V  
0°  
= –5.2 V ±5%) (See Note)  
EE  
13  
12  
14  
15  
25°  
75°  
Characteristic  
Power Supply Current  
Input Current High  
Input Current Low  
High Output Voltage  
Low Output Voltage  
High Input Voltage  
Low Input Voltage  
Symbol Min  
Max  
23  
Min  
—
Max  
21  
Min  
—
Max  
23  
Unit  
I
—
—
mA  
µA  
µA  
E
I
425  
—
—
265  
—
—
265  
—
V
V
V
= PIN 1  
= PIN 16  
= PIN 8  
inH  
CC1  
CC2  
EE  
I
0.5  
0.5  
0.3  
inL  
V
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc  
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc  
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc  
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc  
OH  
V
OL  
V
DIP  
IH  
PIN ASSIGNMENT  
V
IL  
AC PARAMETERS  
Propagation Delay  
Rise Time  
V
A
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
t
0.4  
0.5  
0.5  
1.2  
1.5  
1.5  
0.4  
0.5  
0.5  
1.2  
1.6  
1.6  
0.4  
0.5  
0.5  
1.3  
1.7  
1.7  
ns  
ns  
ns  
pd  
t
r
C
OUT  
OUT  
IN  
OUT  
OUT  
Fall Time  
t
f
C
C
C
A
NOTE:  
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,  
afterthermalequilibriumhasbeenestablished.Thecircuitisinatestsocketormountedonaprintedcircuit  
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through  
a 50–ohm resistor to –2.0 volts.  
A
IN  
A
IN  
IN  
B
B
B
IN  
IN  
IN  
OUT  
B
B
OUT  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
3/93  
Motorola, Inc. 1996  
REV 5  
123

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