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MC10210FN PDF预览

MC10210FN

更新时间: 2024-11-18 22:35:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 栅极触发器逻辑集成电路输出元件
页数 文件大小 规格书
5页 104K
描述
Dual 3-Input/3-Output OR Gate

MC10210FN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, LCC-20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.88
Is Samacsys:N其他特性:3 OUTPUTS EACH FUNCTION
系列:10KJESD-30 代码:S-PQCC-J20
JESD-609代码:e0长度:8.965 mm
逻辑集成电路类型:OR GATE功能数量:2
输入次数:3端子数量:20
最高工作温度:85 °C最低工作温度:-30 °C
输出特性:OPEN-EMITTER封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:-5.2 V
最大电源电流(ICC):42 mAProp。Delay @ Nom-Sup:2.8 ns
传播延迟(tpd):2.8 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:4.57 mm
子类别:Gates表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.965 mm
Base Number Matches:1

MC10210FN 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10210 is designed to drive up to six transmission lines simul–  
taneously. The multiple outputs of this device also allow the wire “OR” –ing of  
several levels of gating for minimization of gate and package count.  
The ability to control three parallel lines with minimum propagation delay  
from a single point makes the MC10210 particularly useful in clock distribution  
applications where minimum clock skew is desired.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P
= 160 mW typ/pkg (No Loads)  
= 1.5 ns typ (All Output Loaded)  
D
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
t
pd  
t , t = 1.5 ns typ (20%–80%)  
r f  
FN SUFFIX  
PLCC  
CASE 775–02  
LOGIC DIAGRAM  
5
2
3
4
6
7
DIP  
PIN ASSIGNMENT  
9
10  
11  
12  
13  
14  
V
A
V
V
B
B
B
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
CC2  
CC1  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
A
A
V
V
V
= PIN 1, 15  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
A
IN  
B
B
B
A
IN  
IN  
IN  
IN  
A
IN  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–36 of the Motorola MECL Data  
Book (DL122/D).  
3/93  
Motorola, Inc. 1996  
REV 5  

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