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MC10198PD PDF预览

MC10198PD

更新时间: 2024-11-19 13:11:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 振荡器预分频器多谐振动器逻辑集成电路输入元件时钟
页数 文件大小 规格书
10页 155K
描述
Monostable Multivibrator, ECL, PDIP16

MC10198PD 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
逻辑集成电路类型:MONOSTABLE MULTIVIBRATOR端子数量:16
最高工作温度:85 °C最低工作温度:-30 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE子类别:Prescaler/Multivibrators
表面贴装:NO技术:ECL
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC10198PD 数据手册

 浏览型号MC10198PD的Datasheet PDF文件第2页浏览型号MC10198PD的Datasheet PDF文件第3页浏览型号MC10198PD的Datasheet PDF文件第4页浏览型号MC10198PD的Datasheet PDF文件第5页浏览型号MC10198PD的Datasheet PDF文件第6页浏览型号MC10198PD的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10198 is a retriggerable monostable multivibrator. Two enable inputs  
permit triggering on any combination of positive or negative edges as shown in  
the accompanying table. The trigger input is buffered by Schmitt triggers  
making it insensitive to input rise and fall times.  
The pulse width is controlled by an external capacitor and resistor. The  
resistor sets a current which is the linear discharge rate of the capacitor. Also,  
the pulse width can be controlled by an external current source or voltage (see  
applications information).  
For high–speed response with minimum delay, a hi–speed input is also  
provided. This input bypasses the internal Schmitt triggers and the output  
responds within 2 nanoseconds typically.  
Output logic and threshold levels are standard MECL 10,000. Test  
conditions are per Table 2. Each “Precondition” referred to in Table 2 is per the  
sequence of Table 1.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
FN SUFFIX  
PLCC  
CASE 775–02  
P
= 415 mW typ/pkg (No Load)  
= 4.0 ns typ Trigger Inpt to Q  
2.0 ns typ Hi–Speed Input to Q  
D
t
pd  
DIP  
PIN ASSIGNMENT  
1
10 ns typ  
Min Timing Pulse Width  
Max Timing Pulse Width  
Min Trigger Pulse Width  
Min Hi–Speed  
Trigger Pulse Width  
Enable Setup Time  
Enable Hold Time  
PW  
PW  
PW  
PW  
Qmin  
Qmax  
T
2
>10 ms typ  
2.0 ns typ  
3.0 ns typ  
V
V
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
CC2  
HS  
HIGH–SPEED  
INPUT  
Q
t
t
1.0 ns typ  
1.0 ns typ  
set  
hold  
Q
N/C  
C
E
TRIGGER INPUT  
N/C  
1
EXT  
C
= 0 (Pin 4 open), R  
= 0  
Ext  
(Pin 6 to V  
Ext  
)
EE  
= 10 µF, R  
POS  
2
C
Ext  
= 2.7 kΩ  
Ext  
R
N/C  
EXT  
EXT.PULSE  
WIDTH CONTROL  
E
NEG  
V
N/C  
EE  
LOGIC DIAGRAM  
V
V
CC  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
6
4
R
C
EXT  
EXT  
E pos  
Q
5
7
3
EXTERNAL PULSE  
WIDTH CONTROL  
TRUTH TABLE  
V
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
INPUT  
OUTPUT  
E
10  
13  
NEG  
E
Pos  
E
Neg  
TRIGGER  
INPUT  
L
L
H
H
L
H
L
Triggers on both positive & negative input slopes  
Triggers on positive input slope  
Triggers on negative input slope  
Trigger is disabled  
Q
2
HI–SPEED  
INPUT  
15  
H
3/93  
Motorola, Inc. 1996  
REV 5  

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