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MC10192FNR2 PDF预览

MC10192FNR2

更新时间: 2024-09-24 14:53:11
品牌 Logo 应用领域
安森美 - ONSEMI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
4页 82K
描述
10K SERIES, QUAD 2-BIT DRIVER, COMPLEMENTARY OUTPUT, PQCC20, PLASTIC, LCC-20

MC10192FNR2 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.48
Is Samacsys:N系列:10K
JESD-30 代码:S-PQCC-J20JESD-609代码:e0
长度:8.965 mm逻辑集成电路类型:BUS DRIVER
位数:2功能数量:4
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-30 °C
输出特性:OPEN-COLLECTOR输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):4.5 ns
认证状态:Not Qualified座面最大高度:4.57 mm
表面贴装:YES技术:ECL
温度等级:OTHER端子面层:Tin/Lead (Sn80Pb20)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.965 mmBase Number Matches:1

MC10192FNR2 数据手册

 浏览型号MC10192FNR2的Datasheet PDF文件第2页浏览型号MC10192FNR2的Datasheet PDF文件第3页浏览型号MC10192FNR2的Datasheet PDF文件第4页 
MC10192  
Quad Bus Driver  
The MC10192 contains four line drivers with complementary  
outputs. Each driver has a Data (D) input and shares an Enable (E)  
input with another driver. The two driver outputs are the uncommitted  
collectors of a pair of NPN transistors operating as a current switch.  
Each driver accepts 10K MECL input signals and provides a nominal  
signal swing of 800 mV across a 50 load at each output collector.  
Outputs can drive higher values of load resistance, provided that the  
http://onsemi.com  
MARKING  
DIAGRAMS  
combination of I drop and load return voltage V does not cause an  
R
LR  
output collector to go more negative than –2.4 V with respect to V  
.
16  
CC  
CDIP–16  
L SUFFIX  
CASE 620  
To avoid output transistor breakdown, the load return voltage should  
MC10192L  
AWLYYWW  
not be more positive than +5.5 V with respect to V . When the E  
CC  
input is high, both output transistors of a driver are nonconducting.  
When not used, the E inputs, as well as the D inputs, may be left open.  
Open Collector Outputs Drive Terminated Lines or  
Transformers  
1
16  
PDIP–16  
P SUFFIX  
CASE 648  
MC10192P  
AWLYYWW  
50 kW Input Pulldown Resistors on All Inputs (Unused  
Inputs May Be Left Open)  
1
1
Power Dissipation = 575 mW typ/pkg (No Load)  
Propagation Delay = 3.5 ns typ (E — Output)  
PLCC–20  
FN SUFFIX  
CASE 775  
10192  
3.0 ns typ (D — Output)  
AWLYYWW  
LOGIC DIAGRAM  
A
= Assembly Location  
E1  
D1  
7
5
3
4
1
2
Z1  
Z1  
Z2  
Z2  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
DIP PIN ASSIGNMENT  
D2  
6
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Z2  
Z2  
Z1  
Z1  
D1  
D2  
E1  
V
CC  
D3 10  
15 Z3  
14 Z3  
13 Z4  
12 Z4  
Z3  
Z3  
Z4  
Z4  
D4  
D3  
E2  
D4 11  
E2  
9
V
= PIN 16  
= PIN 8  
CC  
V
EE  
V
EE  
TRUTH TABLE  
Inputs Output  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables  
on page 18 of the ON Semiconductor MECL Data Book  
(DL122/D).  
E
H
L
D
X
H
L
Z
H
H
L
Z
H
L
L
H
ORDERING INFORMATION  
Note: Unused outputs must be terminated  
to V for proper operation.  
CC  
Device  
Package  
Shipping  
MC10192L  
CDIP–16  
25 Units / Rail  
MC10192P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
MC10192FN  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10192/D  

MC10192FNR2 替代型号

型号 品牌 替代类型 描述 数据表
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