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MC10175P PDF预览

MC10175P

更新时间: 2024-09-22 22:54:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 108K
描述
Quint Latch

MC10175P 技术参数

是否Rohs认证:不符合生命周期:Transferred
包装说明:PLASTIC, DIP-16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.79
Is Samacsys:N其他特性:WITH DUAL LATCH ENABLE; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH
系列:10KJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.175 mm
逻辑集成电路类型:D LATCH位数:5
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-30 °C
输出特性:OPEN-EMITTER输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:-5.2 V
最大电源电流(ICC):107 mA传播延迟(tpd):4.4 ns
认证状态:Not Qualified座面最大高度:4.44 mm
子类别:FF/Latches表面贴装:NO
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
触发器类型:LOW LEVEL宽度:7.62 mm
Base Number Matches:1

MC10175P 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10175 is a high speed, low power quint latch. It features five D type  
latches with common reset and a common two–input clock. Data is transferred  
on the negative edge of the clock and latched on the positive edge. The two  
clock inputs are “OR”ed together.  
Any change on the data input will be reflected at the outputs while the clock  
is low. The outputs are latched on the positive transition of the clock. While the  
clock is in the high state, a change in the information present at the data inputs  
will not affect the output information. The reset input is enabled only when the  
clock is in the high state.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
P
= 400 mW typ/pkg (No Load)  
= 2.5 ns typ (Data to Output)  
D
t
pd  
t , t = 2.0 ns typ (20%–80%)  
r f  
FN SUFFIX  
PLCC  
CASE 775–02  
LOGIC DIAGRAM  
D0 10  
D
C
Q
14 Q0  
15 Q1  
R
R
DIP  
PIN ASSIGNMENT  
D1 12  
D2 13  
D
C
Q
Q
Q
Q
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
Q1  
Q0  
D2  
D1  
Q2  
D
C
2
3
4
Q2  
Q3  
Q4  
Q3  
Q4  
D4  
C0  
C1  
R
R
R
D3  
9
D
C
RESET  
D0  
D3  
V
EE  
D4  
5
D
C
C0  
C1  
6
7
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
RESET 11  
V
TRUTH TABLE  
D
C0  
C1  
Reset  
Q
n+1  
L
H
X
X
X
X
L
L
H
X
H
X
L
L
X
H
X
H
X
X
L
L
H
H
L
H
Q n  
Q n  
L
L
3/93  
Motorola, Inc. 1996  
REV 5  

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