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MC10175P PDF预览

MC10175P

更新时间: 2024-09-23 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 110K
描述
Quint Latch

MC10175P 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.26
Is Samacsys:N系列:10K
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
长度:19.175 mm逻辑集成电路类型:D LATCH
位数:5功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-30 °C输出特性:OPEN-EMITTER
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:-5.2 V
最大电源电流(ICC):107 mA传播延迟(tpd):4.3 ns
认证状态:Not Qualified座面最大高度:4.44 mm
子类别:FF/Latches表面贴装:NO
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:LOW LEVEL
宽度:7.62 mmBase Number Matches:1

MC10175P 数据手册

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MC10175  
Quint Latch  
The MC10175 is a high speed, low power quint latch. It features five  
D type latches with common reset and a common two–input clock.  
Data is transferred on the negative edge of the clock and latched on the  
positive edge. The two clock inputs are “OR”ed together.  
Any change on the data input will be reflected at the outputs while  
the clock is low. The outputs are latched on the positive transition of  
the clock. While the clock is in the high state, a change in the  
information present at the data inputs will not affect the output  
information. The reset input is enabled only when the clock is in the  
high state.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
CDIP–16  
L SUFFIX  
CASE 620  
MC10175L  
AWLYYWW  
P = 400 mW typ/pkg (No Load)  
D
t = 2.5 ns typ (Data to Output)  
pd  
1
t , t = 2.0 ns typ (20%–80%)  
r
f
16  
PDIP–16  
P SUFFIX  
CASE 648  
MC10175P  
AWLYYWW  
LOGIC DIAGRAM  
D0 10  
D
C
Q
Q
Q
Q
Q
14 Q0  
15 Q1  
1
1
R
R
PLCC–20  
FN SUFFIX  
CASE 775  
10175  
D1 12  
D
C
AWLYYWW  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
D2 13  
D
C
2
3
4
Q2  
Q3  
Q4  
WW = Work Week  
R
R
R
DIP PIN ASSIGNMENT  
D3  
9
5
D
C
V
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CC2  
CC1  
Q2  
Q1  
Q0  
Q3  
Q4  
D4  
C0  
C1  
D4  
D
C
C0  
C1  
6
7
D2  
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
V
D1  
CC2  
RESET 11  
V
EE  
RESET  
D0  
TRUTH TABLE  
D3  
V
EE  
D
C0  
C1  
Reset  
Q
n+1  
L
H
X
X
X
X
L
L
H
X
H
X
L
L
X
H
X
H
X
X
L
L
H
H
L
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables  
on page 18 of the ON Semiconductor MECL Data Book  
(DL122/D).  
H
Q n  
Q n  
L
L
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC10175L  
CDIP–16  
25 Units / Rail  
MC10175P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
MC10175FN  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10175/D  

MC10175P 替代型号

型号 品牌 替代类型 描述 数据表
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