MC10175
Quint Latch
The MC10175 is a high speed, low power quint latch. It features five
D type latches with common reset and a common two–input clock.
Data is transferred on the negative edge of the clock and latched on the
positive edge. The two clock inputs are “OR”ed together.
Any change on the data input will be reflected at the outputs while
the clock is low. The outputs are latched on the positive transition of
the clock. While the clock is in the high state, a change in the
information present at the data inputs will not affect the output
information. The reset input is enabled only when the clock is in the
high state.
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MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
MC10175L
AWLYYWW
• P = 400 mW typ/pkg (No Load)
D
• t = 2.5 ns typ (Data to Output)
pd
1
• t , t = 2.0 ns typ (20%–80%)
r
f
16
PDIP–16
P SUFFIX
CASE 648
MC10175P
AWLYYWW
LOGIC DIAGRAM
D0 10
D
C
Q
Q
Q
Q
Q
14 Q0
15 Q1
1
1
R
R
PLCC–20
FN SUFFIX
CASE 775
10175
D1 12
D
C
AWLYYWW
A
= Assembly Location
WL = Wafer Lot
YY = Year
D2 13
D
C
2
3
4
Q2
Q3
Q4
WW = Work Week
R
R
R
DIP PIN ASSIGNMENT
D3
9
5
D
C
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
CC1
Q2
Q1
Q0
Q3
Q4
D4
C0
C1
D4
D
C
C0
C1
6
7
D2
V
= PIN 1
= PIN 16
= PIN 8
CC1
V
D1
CC2
RESET 11
V
EE
RESET
D0
TRUTH TABLE
D3
V
EE
D
C0
C1
Reset
Q
n+1
L
H
X
X
X
X
L
L
H
X
H
X
L
L
X
H
X
H
X
X
L
L
H
H
L
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
H
Q n
Q n
L
L
ORDERING INFORMATION
Device
Package
Shipping
MC10175L
CDIP–16
25 Units / Rail
MC10175P
PDIP–16
PLCC–20
25 Units / Rail
46 Units / Rail
MC10175FN
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
January, 2002 – Rev. 7
MC10175/D