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MC10111LDS PDF预览

MC10111LDS

更新时间: 2024-11-28 12:58:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA
页数 文件大小 规格书
4页 82K
描述
NOR Gate, ECL, CDIP16

MC10111LDS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-XDIP-T16
JESD-609代码:e0逻辑集成电路类型:NOR GATE
端子数量:16最高工作温度:85 °C
最低工作温度:-30 °C封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:-5.2 V施密特触发器:NO
子类别:Gates表面贴装:NO
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

MC10111LDS 数据手册

 浏览型号MC10111LDS的Datasheet PDF文件第2页浏览型号MC10111LDS的Datasheet PDF文件第3页浏览型号MC10111LDS的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10111 is designed to drive up to three transmission lines simul–  
taneously. The multiple outputs of this device also allow the wire “OR”–ing of  
several levels of gating for minimization of gate and package count.  
The ability to control three parallel lines from a single point makes the  
MC10111 particularly useful in clock distribution applications where minimum  
clock skew is desired. Three V  
used.  
pins are provided and each one should be  
CC  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P
= 80 mW typ/gate (No Load)  
= 2.4 ns typ (All Outputs Loaded)  
D
t
pd  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
t , t = 2.2 ns typ (20%–80%)  
r f  
LOGIC DIAGRAM  
DIP  
PIN ASSIGNMENT  
2
3
4
5
6
7
V
A
V
V
B
B
B
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
CC2  
CC1  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
12  
13  
14  
A
A
9
10  
11  
A
IN  
V
V
V
= PIN 1,15  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
B
B
B
A
IN  
IN  
IN  
IN  
A
IN  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
9/96  
Motorola, Inc. 1996  
REV 6  

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