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MC10111 PDF预览

MC10111

更新时间: 2024-11-27 22:54:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA
页数 文件大小 规格书
4页 82K
描述
Dual 3-Input/3-Output NOR Gate

MC10111 数据手册

 浏览型号MC10111的Datasheet PDF文件第2页浏览型号MC10111的Datasheet PDF文件第3页浏览型号MC10111的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10111 is designed to drive up to three transmission lines simul–  
taneously. The multiple outputs of this device also allow the wire “OR”–ing of  
several levels of gating for minimization of gate and package count.  
The ability to control three parallel lines from a single point makes the  
MC10111 particularly useful in clock distribution applications where minimum  
clock skew is desired. Three V  
used.  
pins are provided and each one should be  
CC  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P
= 80 mW typ/gate (No Load)  
= 2.4 ns typ (All Outputs Loaded)  
D
t
pd  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
t , t = 2.2 ns typ (20%–80%)  
r f  
LOGIC DIAGRAM  
DIP  
PIN ASSIGNMENT  
2
3
4
5
6
7
V
A
V
V
B
B
B
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
CC2  
CC1  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
12  
13  
14  
A
A
9
10  
11  
A
IN  
V
V
V
= PIN 1,15  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
B
B
B
A
IN  
IN  
IN  
IN  
A
IN  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
9/96  
Motorola, Inc. 1996  
REV 6  

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