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MC10110L PDF预览

MC10110L

更新时间: 2024-11-28 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
8页 70K
描述
Dual 3-Input/3-Output OR Gate

MC10110L 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.85
系列:10KJESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.495 mm
逻辑集成电路类型:OR GATE功能数量:2
输入次数:3端子数量:16
最高工作温度:85 °C最低工作温度:-30 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:-5.2 V最大电源电流(ICC):42 mA
Prop。Delay @ Nom-Sup:3.8 ns传播延迟(tpd):3.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
表面贴装:NO技术:ECL
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MC10110L 数据手册

 浏览型号MC10110L的Datasheet PDF文件第2页浏览型号MC10110L的Datasheet PDF文件第3页浏览型号MC10110L的Datasheet PDF文件第4页浏览型号MC10110L的Datasheet PDF文件第5页浏览型号MC10110L的Datasheet PDF文件第6页浏览型号MC10110L的Datasheet PDF文件第7页 
The ability to control three parallel lines from a single point makes  
the MC10110 particularly useful in clock distribution applications  
where minimum clock skew is desired. Three V  
and each one should be used.  
pins are provided  
CC  
http://onsemi.com  
P = 80 mW typ/pkg (No Load)  
D
MARKING  
DIAGRAMS  
t = 2.4 ns typ (All Outputs Loaded)  
pd  
t , t = 2.2 ns typ (20%–80%)  
r f  
16  
CDIP–16  
L SUFFIX  
CASE 620  
MC10110L  
AWLYYWW  
LOGIC DIAGRAM  
5
6
7
1
2
3
4
16  
PDIP–16  
P SUFFIX  
CASE 648  
MC10110P  
AWLYYWW  
9
10  
11  
12  
13  
14  
1
1
V
= PIN 1, 15  
= PIN 16  
= PIN 8  
CC1  
V
PLCC–20  
FN SUFFIX  
CASE 775  
CC2  
10101  
V
EE  
AWLYYWW  
DIP  
PIN ASSIGNMENT  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
V
CC1  
A
OUT  
B
OUT  
A
OUT  
ORDERING INFORMATION  
B
OUT  
A
OUT  
Device  
Package  
Shipping  
B
OUT  
A
IN  
MC10110L  
CDIP–16  
25 Units / Rail  
B
IN  
A
IN  
MC10110P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
B
IN  
A
IN  
MC10110FN  
B
IN  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 7  
MC10110/D  

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