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MC10107_02 PDF预览

MC10107_02

更新时间: 2024-11-25 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
8页 109K
描述
Triple 2-Input Exclusive OR/ Exclusive NOR Gate

MC10107_02 数据手册

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MC10107  
Triple 2-Input Exclusive OR/  
Exclusive NOR Gate  
The MC10107 is a triple–2 input exclusive OR/NOR gate.  
P = 40 mW typ/gate (No Load)  
D
t = 2.8 ns typ  
pd  
http://onsemi.com  
t , t = 2.5 ns typ (20%–80%)  
r
f
MARKING  
DIAGRAMS  
LOGIC DIAGRAM  
4
5
2
3
16  
CDIP–16  
L SUFFIX  
CASE 620  
MC10107L  
AWLYYWW  
9
7
11  
10  
1
14  
15  
12  
13  
16  
PDIP–16  
P SUFFIX  
CASE 648  
MC10107P  
AWLYYWW  
3 = (4 5) + (4 5)  
2 = (4 5) + (4 5)  
1
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
1
CC2  
V
EE  
PLCC–20  
FN SUFFIX  
CASE 775  
10107  
AWLYYWW  
DIP  
PIN ASSIGNMENT  
V
A
V
CC2  
A
= Assembly Location  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
C
C
C
C
B
IN  
OUT  
A
OUT  
IN  
A
IN  
OUT  
OUT  
ORDERING INFORMATION  
A
IN  
Device  
Package  
Shipping  
*NC  
OUT  
OUT  
IN  
MC10107L  
CDIP–16  
25 Units / Rail  
B
B
B
IN  
MC10107P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
V
EE  
MC10107FN  
*NC = No Connection  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10107/D  

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