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MC10104 PDF预览

MC10104

更新时间: 2024-11-24 22:54:59
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
5页 106K
描述
Quad 2-Input AND Gate

MC10104 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10104 is a quad 2–input AND gate. One of the gates has both  
AND/NAND outputs available.  
P
= 35 mW typ/gate (No Load)  
= 2.7 ns typ  
D
t
pd  
t , t = 2.0 ns typ (20%–80%)  
r f  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
LOGIC DIAGRAM  
FN SUFFIX  
PLCC  
CASE 775–02  
4
5
2
3
DIP  
PIN ASSIGNMENT  
6
7
V
A
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
10  
11  
14  
D
C
D
D
OUT  
OUT  
IN  
OUT  
OUT  
12  
13  
9
B
15  
A
IN  
A
IN  
IN  
V
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
C
C
D
B
IN  
IN  
B
IN  
IN  
V
OUT  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
3/93  
Motorola, Inc. 1996  
REV 5  

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