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MC10103P PDF预览

MC10103P

更新时间: 2024-11-25 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI 逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 107K
描述
Quad 2-Input OR Gate

MC10103P 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.51
系列:10KJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.175 mm
逻辑集成电路类型:OR GATE功能数量:4
输入次数:2端子数量:16
最高工作温度:85 °C最低工作温度:-30 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:-5.2 V最大电源电流(ICC):29 mA
Prop。Delay @ Nom-Sup:3.3 ns传播延迟(tpd):2.9 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:4.44 mm子类别:Gates
表面贴装:NO技术:ECL
温度等级:OTHER端子面层:Tin/Lead (Sn80Pb20)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MC10103P 数据手册

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MC10103  
Quad 2-Input OR Gate  
The MC10103 is a quad 2–input OR gate. The MC10103 provides  
one gate with OR/NOR outputs.  
P = 25 mW typ/gate (No Load)  
D
t = 2.0 ns typ  
pd  
http://onsemi.com  
t , t = 2.0 ns typ (20%–80%)  
r
f
LOGIC DIAGRAM  
MARKING  
DIAGRAMS  
4
5
2
16  
CDIP–16  
L SUFFIX  
CASE 620  
MC10103L  
AWLYYWW  
6
7
3
1
12  
13  
15  
9
16  
10  
11  
PDIP–16  
P SUFFIX  
CASE 648  
MC10103P  
AWLYYWW  
14  
V
V
= PIN 1  
= PIN 16  
= PIN 8  
1
CC1  
CC2  
1
V
EE  
PLCC–20  
FN SUFFIX  
CASE 775  
10103  
AWLYYWW  
DIP  
PIN ASSIGNMENT  
A
= Assembly Location  
V
A
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
C
D
C
C
D
D
C
OUT  
OUT  
OUT  
B
OUT  
IN  
A
IN  
ORDERING INFORMATION  
A
IN  
IN  
Device  
Package  
Shipping  
B
IN  
IN  
MC10103L  
CDIP–16  
25 Units / Rail  
B
IN  
IN  
MC10103P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
V
OUT  
EE  
MC10103FN  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10103/D  

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