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MC10101FN PDF预览

MC10101FN

更新时间: 2024-01-07 18:32:41
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
8页 108K
描述
Quad OR/NOR Gate

MC10101FN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
逻辑集成电路类型:OR/NOR GATE端子数量:16
最高工作温度:85 °C最低工作温度:-30 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:-5.2 V
认证状态:Not Qualified施密特触发器:NO
子类别:Gates表面贴装:NO
技术:ECL10K温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

MC10101FN 数据手册

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MC10101  
Quad OR/NOR Gate  
The MC10101 is a quad 2–input OR/NOR gate with one input from  
each gate common to pin 12.  
P = 25 mW typ/gate (No Load)  
D
t = 2.0 ns typ  
pd  
http://onsemi.com  
t , t = 2.0 ns typ (20%–80%)  
r
f
LOGIC DIAGRAM  
MARKING  
DIAGRAMS  
4
7
2
5
16  
CDIP–16  
L SUFFIX  
CASE 620  
MC10101L  
AWLYYWW  
3
6
1
10  
14  
11  
16  
PDIP–16  
P SUFFIX  
CASE 648  
MC10101P  
AWLYYWW  
13  
12  
15  
9
1
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
1
CC2  
V
EE  
PLCC–20  
FN SUFFIX  
CASE 775  
10101  
AWLYYWW  
DIP  
PIN ASSIGNMENT  
A
= Assembly Location  
V
A
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
WL = Wafer Lot  
YY = Year  
WW = Work Week  
CC1  
D
OUT  
C
OUT  
D
IN  
OUT  
OUT  
B
A
IN  
ORDERING INFORMATION  
COMMON  
INPUT  
A
OUT  
B
OUT  
Device  
Package  
Shipping  
C
OUT  
MC10101L  
CDIP–16  
25 Units / Rail  
C
IN  
B
IN  
MC10101P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
D
OUT  
V
EE  
MC10101FN  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10101/D  

MC10101FN 替代型号

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