5秒后页面跳转
捷配首页

Datasheet > MC100EP809MNR4G
MC100EP809MNR4G PDF预览

MC100EP809MNR4G

更新时间： 2024-01-26 11:49:11
品牌 Logo 应用领域
安森美 - ONSEMI 驱动逻辑集成电路
页数 文件大小 规格书
10页 112K
描述
Differentia HSTL/PECL/LVDS to HSTL Clock Driver

阅读下载

中文翻译

获取价格

MC100EP809MNR4G 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：VQCCN, LCC32,.2SQ,20针数：32
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.81系列：100E
输入调节：DIFFERENTIAL MUXJESD-30 代码：S-PQCC-N32
JESD-609代码：e3长度：5 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER湿度敏感等级：1
功能数量：1反相输出次数：
端子数量：32实输出次数：9
最高工作温度：85 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：VQCCN
封装等效代码：LCC32,.2SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.8,3.3 VProp。Delay @ Nom-Sup：1.11 ns
传播延迟（tpd）：1 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.05 ns座面最大高度：1 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：ECL
温度等级：COMMERCIAL EXTENDED端子面层：Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5 mm最小 fmax：500 MHz

MC100EP809MNR4G 数据手册

 浏览型号MC100EP809MNR4G的Datasheet PDF文件第2页浏览型号MC100EP809MNR4G的Datasheet PDF文件第3页浏览型号MC100EP809MNR4G的Datasheet PDF文件第4页浏览型号MC100EP809MNR4G的Datasheet PDF文件第5页浏览型号MC100EP809MNR4G的Datasheet PDF文件第6页浏览型号MC100EP809MNR4G的Datasheet PDF文件第7页 
MC100EP809  
3.3Vꢀ2:1:9 Differential  
HSTL/PECL/LVDS to HSTL  
Clock Driver with LVTTL  
Clock Select and Enable  
www.onsemi.com  
MARKING  
Description  
The MC100EP809 is a low skew 2:1:9 differential clock driver,  
designed with clock distribution in mind, accepting two clock sources  
into an input multiplexer. The part is designed for use in low voltage  
applications which require a large number of outputs to drive precisely  
aligned low skew signals to their destination. The two clock inputs are  
one differential HSTL and one differential LVPECL. Both input pairs  
can accept LVDS levels. They are selected by the CLK_SEL pin  
which is LVTTL. To avoid generation of a runt clock pulse when the  
device is enabled/disabled, the Output Enable (OE), which is LVTTL,  
is synchronous ensuring the outputs will only be enabled/disabled  
when they are already in LOW state (Figure 9).  
DIAGRAMS*  
MC100  
EP809  
32−LEAD LQFP  
FA SUFFIX  
CASE 873A  
AWLYYWWG  
32  
1
1
The MC100EP809 guarantees low output−to−output skew. The  
optimal design, layout, and processing minimize skew within a device  
and from lot to lot. The MC100EP809 output structure uses open  
emitter architecture and will be terminated with 50 ꢀ to ground  
instead of a standard HSTL configuration (Figure 7). To ensure the  
tight skew specification is realized, both sides of the differential output  
need to be terminated identically into 50 ꢀ even if only one output is  
being used. If an output pair is unused, both outputs may be left open  
(unterminated) without affecting skew.  
Designers can take advantage of the EP809’s performance to  
distribute low skew clocks across the backplane of the board. Both  
clock inputs may be single−end driven by biasing the non−driven pin  
in an input pair (Figure 8).  
MC100  
EP809  
32  
1
AWLYYWWG  
QFN32  
MN SUFFIX  
CASE 488AM  
G
A
= Assembly Location  
= Wafer Lot  
WL  
YY  
WW  
= Year  
= Work Week  
G or G = Pb−Free Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
Features  
• 100 ps Typical Device−to−Device Skew  
• 15 ps Typical within Device Skew  
• HSTL Compatible Outputs Drive 50 ꢀ to GND with no  
Offset Voltage  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
• Maximum Frequency > 750 MHz  
• 850 ps Typical Propagation Delay  
• Fully Compatible with Micrel SY89809L  
• PECL and HSTL Mode Operating Range: V  
= 3 V to 3.6 V  
CCI  
with GND = 0 V, V  
= 1.6 V to 2.0 V  
CCO  
• Open Input Default State  
• These Devices are Pb−Free and are RoHS Compliant  
© Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
April, 2015 − Rev. 10  
MC100EP809/D  
1234567...10

中文翻译

下载PDF

MC100EP809MNR4G 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP210SMNG ONSEMI

类似代替

 2.5V 1:5 Dual Differential LVDS Compatible Clock Driver
MC100LVEL14DWG ONSEMI

功能相似

 3.3V ECL 1:5 Clock Distribution Chip
MC100LVEP111FAG ONSEMI

功能相似

 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver

与MC100EP809MNR4G相关器件

型号 品牌 获取价格 描述 数据表
MC100EP89D ONSEMI

获取价格

 		Evaluation Board Manual for High Frequency SOIC 8
MC100EP90 ONSEMI

获取价格

 		-3.3V / -5V Triple ECL Input to LVPECL/PECL Output Translator
MC100EP90D MOTOROLA

获取价格

 		ECL to PECL Translator, 3 Func, Complementary Output, ECL, PDSO20, PLASTIC, SOIC-20
MC100EP90DT ONSEMI

获取价格

 		−3.3V / −5V Triple ECL Input to LVPECL/PECL Output Translator
MC100EP90DTG ONSEMI

获取价格

 		−3.3V / −5V Triple ECL Input to LVPECL/PECL Output Translator
MC100EP90DTR2 ONSEMI

获取价格

 		−3.3V / −5V Triple ECL Input to LVPECL/PECL Output Translator
MC100EP90DTR2G ONSEMI

获取价格

 		−3.3V / −5V Triple ECL Input to LVPECL/PECL Output Translator
MC100EP91 ONSEMI

获取价格

 		2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator
MC100EP91DW ONSEMI

获取价格

 		2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator
MC100EP91DWG ONSEMI

获取价格

 		2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator

与MC100EP809MNR4G相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证