Datasheet > MC100EP809MNG

MC100EP809MNG

更新时间： 2024-10-01 01:11:35

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
10页	112K
描述
Differentia HSTL/PECL/LVDS to HSTL Clock Driver

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MC100EP809MNG 数据手册

MC100EP809

3.3Vꢀ2:1:9 Differential

HSTL/PECL/LVDS to HSTL

Clock Driver with LVTTL

Clock Select and Enable

www.onsemi.com

MARKING

Description

The MC100EP809 is a low skew 2:1:9 differential clock driver,

designed with clock distribution in mind, accepting two clock sources

into an input multiplexer. The part is designed for use in low voltage

applications which require a large number of outputs to drive precisely

aligned low skew signals to their destination. The two clock inputs are

one differential HSTL and one differential LVPECL. Both input pairs

can accept LVDS levels. They are selected by the CLK_SEL pin

which is LVTTL. To avoid generation of a runt clock pulse when the

device is enabled/disabled, the Output Enable (OE), which is LVTTL,

is synchronous ensuring the outputs will only be enabled/disabled

when they are already in LOW state (Figure 9).

DIAGRAMS*

MC100

EP809

32−LEAD LQFP

FA SUFFIX

CASE 873A

AWLYYWWG

The MC100EP809 guarantees low output−to−output skew. The

optimal design, layout, and processing minimize skew within a device

and from lot to lot. The MC100EP809 output structure uses open

emitter architecture and will be terminated with 50 ꢀ to ground

instead of a standard HSTL configuration (Figure 7). To ensure the

tight skew specification is realized, both sides of the differential output

need to be terminated identically into 50 ꢀ even if only one output is

being used. If an output pair is unused, both outputs may be left open

(unterminated) without affecting skew.

Designers can take advantage of the EP809’s performance to

distribute low skew clocks across the backplane of the board. Both

clock inputs may be single−end driven by biasing the non−driven pin

in an input pair (Figure 8).

MC100

EP809

AWLYYWWG

QFN32

MN SUFFIX

CASE 488AM

= Assembly Location

= Wafer Lot

= Year

= Work Week

G or G = Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

Features

• 100 ps Typical Device−to−Device Skew

• 15 ps Typical within Device Skew

• HSTL Compatible Outputs Drive 50 ꢀ to GND with no

Offset Voltage

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

• Maximum Frequency > 750 MHz

• 850 ps Typical Propagation Delay

• Fully Compatible with Micrel SY89809L

• PECL and HSTL Mode Operating Range: V

= 3 V to 3.6 V

CCI

with GND = 0 V, V

= 1.6 V to 2.0 V

CCO

• Open Input Default State

• These Devices are Pb−Free and are RoHS Compliant

Publication Order Number:

April, 2015 − Rev. 10

MC100EP809/D

12 3 4 5 6 7...10

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MC100EP809MNG 替代型号

型号	品牌	替代类型	描述	数据表
MC100LVEL14DWG	ONSEMI	功能相似	3.3V ECL 1:5 Clock Distribution Chip
MC100LVEP14DTG	ONSEMI	功能相似	2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver
MC100LVEP111FAG	ONSEMI	功能相似	2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver

与MC100EP809MNG相关器件

型号	品牌	获取价格	描述	数据表
MC100EP809MNR4G	ONSEMI	获取价格	Differentia HSTL/PECL/LVDS to HSTL Clock Driver
MC100EP89D	ONSEMI	获取价格	Evaluation Board Manual for High Frequency SOIC 8
MC100EP90	ONSEMI	获取价格	-3.3V / -5V Triple ECL Input to LVPECL/PECL Output Translator
MC100EP90D	MOTOROLA	获取价格	ECL to PECL Translator, 3 Func, Complementary Output, ECL, PDSO20, PLASTIC, SOIC-20
MC100EP90DT	ONSEMI	获取价格	−3.3V / −5V Triple ECL Input to LVPECL/PECL Output Translator
MC100EP90DTG	ONSEMI	获取价格	−3.3V / −5V Triple ECL Input to LVPECL/PECL Output Translator
MC100EP90DTR2	ONSEMI	获取价格	−3.3V / −5V Triple ECL Input to LVPECL/PECL Output Translator
MC100EP90DTR2G	ONSEMI	获取价格	−3.3V / −5V Triple ECL Input to LVPECL/PECL Output Translator
MC100EP91	ONSEMI	获取价格	2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator
MC100EP91DW	ONSEMI	获取价格	2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator

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