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MC100EP809FAR2G

更新时间： 2024-01-31 01:11:32
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器逻辑集成电路
页数 文件大小 规格书
9页 138K
描述
3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable

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中文翻译

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MC100EP809FAR2G 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP32,.35SQ,32针数：32
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.72
Is Samacsys：N系列：100E
输入调节：DIFFERENTIAL MUXJESD-30 代码：S-PQFP-G32
JESD-609代码：e3长度：7 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER湿度敏感等级：2
功能数量：1反相输出次数：
端子数量：32实输出次数：9
最高工作温度：85 °C最低工作温度：
输出特性：OPEN-EMITTER封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP32,.35SQ,32
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：260电源：1.8,3.3 V
传播延迟（tpd）：1 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.05 ns座面最大高度：1.6 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：ECL
温度等级：COMMERCIAL EXTENDED端子面层：Tin (Sn)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：7 mm最小 fmax：500 MHz
Base Number Matches：1

MC100EP809FAR2G 数据手册

 浏览型号MC100EP809FAR2G的Datasheet PDF文件第2页浏览型号MC100EP809FAR2G的Datasheet PDF文件第3页浏览型号MC100EP809FAR2G的Datasheet PDF文件第4页浏览型号MC100EP809FAR2G的Datasheet PDF文件第5页浏览型号MC100EP809FAR2G的Datasheet PDF文件第6页浏览型号MC100EP809FAR2G的Datasheet PDF文件第7页 
MC100EP809  
3.3Vꢀ1:9 Differential  
HSTL/PECL to HSTL Clock  
Driver with LVTTL Clock  
Select and Enable  
http://onsemi.com  
MARKING  
Description  
The MC100EP809 is a low skew 1−to−9 differential clock driver,  
designed with clock distribution in mind, accepting two clock sources into  
an input multiplexer. The part is designed for use in low voltage  
applications which require a large number of outputs to drive precisely  
aligned low skew signals to their destination. The two clock inputs are  
differential HSTL or PECL and they are selected by the CLK_SEL pin  
which is LVTTL. To avoid generation of a runt clock pulse when the  
device is enabled/disabled, the Output Enable (OE), which is LVTTL, is  
synchronous ensuring the outputs will only be enabled/disabled when they  
are already in LOW state (Figure 8).  
DIAGRAM*  
MC100  
EP809  
AWLYYWWG  
32−LEAD LQFP  
FA SUFFIX  
32  
CASE 873A  
1
The MC100EP809 guarantees low output−to−output skew. The optimal  
design, layout, and processing minimize skew within a device and from lot  
to lot. The MC100EP809 output structure uses open emitter architecture  
and will be terminated with 50 ꢀ to ground instead of a standard HSTL  
configuration (Figure 6). To ensure the tight skew specification is realized,  
both sides of the differential output need to be terminated identically into  
50 ꢀ even if only one output is being used. If an output pair is unused,  
both outputs may be left open (unterminated) without affecting skew.  
Designers can take advantage of the EP809’s performance to  
distribute low skew clocks across the backplane of the board. HSTL  
clock inputs may be driven single−end by biasing the non−driven pin  
in an input pair (Figure 7).  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
WL  
YY  
WW  
G
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
Features  
• 100 ps Typical Device−to−Device Skew  
• 15 ps Typical within Device Skew  
• HSTL Compatible Outputs Drive 50 ꢀ to GND with no  
Offset Voltage  
• Maximum Frequency > 750 MHz  
• 850 ps Typical Propagation Delay  
• Fully Compatible with Micrel SY89809L  
• PECL and HSTL Mode Operating Range: V  
= 3 V to 3.6 V  
CCI  
with GND = 0 V, V  
= 1.6 V to 2.0 V  
CCO  
• Open Input Default State  
• Pb−Free Packages are Available  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 7  
MC100EP809/D  
1234567...9

中文翻译

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MC100EP809FAR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC100LVEP111FAG ONSEMI

类似代替

 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver
MC100LVEP14DTR2G ONSEMI

功能相似

 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver
CY2308SXI-2 CYPRESS

功能相似

 3.3V Zero Delay Buffer

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