Datasheet > 逻辑 > 延迟线> MC100EP195MNG

MC100EP195MNG

更新时间： 2024-10-31 04:17:35

品牌	Logo	应用领域
安森美 - ONSEMI		延迟线逻辑集成电路
页数	文件大小	规格书
20页	220K
描述
3.3V ECL Programmable Delay Chip

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MC100EP195MNG 技术参数

是否无铅：	不含铅	生命周期：	Active
零件包装代码：	QFN	包装说明：	HVQCCN, LCC32,.2SQ,20
针数：	32	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	0.71	Is Samacsys：	N
其他特性：	NECL MODE: VCC=0 WITH VEE= -3.0V TO -3.6V	系列：	100E
JESD-30 代码：	S-XQCC-N32	JESD-609代码：	e3
长度：	5 mm	逻辑集成电路类型：	ACTIVE DELAY LINE
湿度敏感等级：	1	功能数量：	1
抽头/阶步数：	1023	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出极性：	COMPLEMENTARY	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC32,.2SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	-4.5 V
最大电源电流（ICC）：	175 mA	可编程延迟线：	YES
Prop。Delay @ Nom-Sup：	15.8 ns	认证状态：	Not Qualified
座面最大高度：	1 mm	子类别：	Delay Lines
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	ECL	温度等级：	INDUSTRIAL
端子面层：	Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	总延迟标称（td）：	12.2 ns
宽度：	5 mm	Base Number Matches：	1

MC100EP195MNG 数据手册

MC10EP195, MC100EP195

3.3V ECL Programmable

Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC)

designed primarily for clock deskewing and timing adjustment. It

provides variable delay of a differential NECL/PECL input transition.

The delay section consists of a programmable matrix of gates and

multiplexers as shown in the logic diagram, Figure 3. The delay

increment of the EP195 has a digitally selectable resolution of about

10 ps and a net range of up to 10.2 ns. The required delay is selected by

the 10 data select inputs D[9:0] values and controlled by the LEN

(pin 10). A LOW level on LEN allows a transparent LOAD mode of

real time delay values by D[9:0]. A LOW to HIGH transition on LEN

will LOCK and HOLD current values present against any subsequent

changes in D[10:0]. The approximate delay values for varying tap

numbers correlating to D0 (LSB) through D9 (MSB) are shown in

Table 6 and Figure 4.

http://onsemi.com

MARKING

DIAGRAM*

MCXXX

EP195

AWLYYWWG

LQFP−32

FA SUFFIX

CASE 873A

Because the EP195 is designed using a chain of multiplexers it has a

fixed minimum delay of 2.2 ns. An additional pin D10 is provided for

controlling Pins 14 and 15, CASCADE and CASCADE, also latched

by LEN, in cascading multiple PDCs for increased programmable

range. The cascade logic allows full control of multiple PDCs.

Switching devices from all “1” states on D[0:9] with SETMAX LOW

to all “0” states on D[0:9] with SETMAX HIGH will increase the

delay equivalent to “D0”, the minimum increment.

MCXXX

EP195

QFN32

MN SUFFIX

CASE 488AM

AWLYYWWG

Select input pins D[10:0] may be threshold controlled by

combinations of interconnects between V (pin 7) and V (pin 8)

XXX

= 10 or 100

= Assembly Location

for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input

levels, leave V and V open. For ECL operation, short V and

WL, L = Wafer Lot

YY, Y

(Pins 7 and 8). For LVTTL level operation, connect a 1.5 V

= Year

supply reference to V and leave open V pin. The 1.5 V reference

WW, W = Work Week

G or G = Pb−Free Package

voltage to V pin can be accomplished by placing a 2.2 kW resistor

(Note: Microdot may be in either location)

between V and V for a 3.3 V power supply.

*For additional marking information, refer to

Application Note AND8002/D.

The V pin, an internally generated voltage supply, is available to

this device only. For single−ended input conditions, the unused

differential input is connected to V as a switching reference voltage.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 17 of this data sheet.

may also rebias AC coupled inputs. When used, decouple V

and V via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, V should be left open.

The 100 Series contains temperature compensation.

• Maximum Input Clock Frequency >1.2 GHz Typical

• Programmable Range: 0 ns to 10 ns

• Delay Range: 2.2 ns to 12.2 ns

• Open Input Default State

• Safety Clamp on Inputs

• A Logic High on the EN Pin Will Force Q to Logic

Low

• 10 ps Increments

• PECL Mode Operating Range:

• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL

Inputs

= 3.0 V to 3.6 V with V = 0 V

• V Output Reference Voltage

• Pb−Free Packages are Available

• NECL Mode Operating Range:

= 0 V with V = −3.0 V to −3.6 V

Publication Order Number:

December, 2006 − Rev. 16

MC10EP195/D

12 3 4 5 6 7...20

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MC100EP195MNG 替代型号

型号	品牌	替代类型	描述	数据表
MC100EP195BFAG	ONSEMI	完全替代	3.3V ECL Programmable Delay Chip
MC100EP196FAG	ONSEMI	完全替代	3.3V ECL Programmable Delay Chip with FTUNE
MC100EP195FAG	ONSEMI	完全替代	3.3V ECL Programmable Delay Chip

与MC100EP195MNG相关器件

型号	品牌	获取价格	描述	数据表
MC100EP195MNR4G	ONSEMI	获取价格	3.3V ECL Programmable Delay Chip
MC100EP196	ONSEMI	获取价格	3.3V ECL Programmable Delay Chip with FTUNE
MC100EP196_06	ONSEMI	获取价格	3.3V ECL Programmable Delay Chip with FTUNE
MC100EP196A	ONSEMI	获取价格	3.3 V ECL Programmable Delay Chip
MC100EP196AMNG	ONSEMI	获取价格	3.3 V ECL Programmable Delay Chip
MC100EP196AMNR4G	ONSEMI	获取价格	IC ACTIVE DELAY LINE, Delay Line
MC100EP196B	ONSEMI	获取价格	3.3 V ECL Programmable Delay Chip With FTUNE
MC100EP196BFA	ONSEMI	获取价格	3.3 V ECL Programmable Delay Chip With FTUNE
MC100EP196BFAG	ONSEMI	获取价格	3.3 V ECL Programmable Delay Chip With FTUNE
MC100EP196BFAR2	ONSEMI	获取价格	3.3 V ECL Programmable Delay Chip With FTUNE

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