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MC100EP195BFAG

更新时间： 2024-10-31 11:10:59
品牌 Logo 应用领域
安森美 - ONSEMI 延迟线逻辑集成电路
页数 文件大小 规格书
17页 184K
描述
3.3V ECL Programmable Delay Chip

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MC100EP195BFAG 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：QFP包装说明：LEAD FREE, LQFP-32
针数：32Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.92其他特性：NECL MODE: VCC=0 WITH VEE=-3.0 V TO -3.6 V
系列：100EJESD-30 代码：S-PQFP-G32
JESD-609代码：e3长度：7 mm
逻辑集成电路类型：ACTIVE DELAY LINE湿度敏感等级：2
功能数量：1抽头/阶步数：1023
端子数量：32最高工作温度：85 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP32,.35SQ,32封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：260
电源：-4.5 V最大电源电流（ICC）：170 mA
可编程延迟线：YESProp。Delay @ Nom-Sup：15.25 ns
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Delay Lines最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：ECL
温度等级：INDUSTRIAL端子面层：Tin (Sn)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
总延迟标称（td）：12.2 ns宽度：7 mm
Base Number Matches：1

MC100EP195BFAG 数据手册

 浏览型号MC100EP195BFAG的Datasheet PDF文件第2页浏览型号MC100EP195BFAG的Datasheet PDF文件第3页浏览型号MC100EP195BFAG的Datasheet PDF文件第4页浏览型号MC100EP195BFAG的Datasheet PDF文件第5页浏览型号MC100EP195BFAG的Datasheet PDF文件第6页浏览型号MC100EP195BFAG的Datasheet PDF文件第7页 
MC100EP195B  
3.3V ECL Programmable  
Delay Chip  
Descriptions  
The MC100EP195B is a Programmable Delay Chip (PDC)  
designed primarily for clock deskewing and timing adjustment. It  
provides variable delay of a differential NECL/PECL input transition.  
The delay section consists of a programmable matrix of gates and  
multiplexers as shown in the logic diagram, Figure 2. The delay  
increment of the EP195B has a digitally selectable resolution of about  
10 ps and a net range of up to 10.2 ns. The required delay is selected by  
the 10 data select inputs D[9:0] values and controlled by the LEN  
(pin 10). A LOW level on LEN allows a transparent LOAD mode of  
real time delay values by D[9:0]. A LOW to HIGH transition on LEN  
will LOCK and HOLD current values present against any subsequent  
changes in D[10:0]. The approximate delay values for varying tap  
numbers correlating to D0 (LSB) through D9 (MSB) are shown in  
Table 6 and Figure 3.  
http://onsemi.com  
MARKING  
DIAGRAMS*  
MC100  
EP195B  
AWLYYWWG  
LQFP−32  
FA SUFFIX  
CASE 873A  
32  
1
The IN/IN inputs can accept LVPECL (SE of Diff), or LVDS level  
signals. Because the EP195B is designed using a chain of multiplexers  
it has a fixed minimum delay of 2.2 ns. An additional pin D10 is  
provided for controlling Pins 14 and 15, CASCADE and CASCADE,  
also latched by LEN, in cascading multiple PDCs for increased  
programmable range. The cascade logic allows full control of multiple  
PDCs. Switching devices from all “1” states on D[0:9] with SETMAX  
LOW to all “0” states on D[0:9] with SETMAX HIGH will increase  
the delay equivalent to “D0”, the minimum increment.  
1
MC100  
EP195B  
ALYWG  
32  
1
QFN32  
MN SUFFIX  
CASE 488AM  
Select input pins D[10:0] may be threshold controlled by  
A
= Assembly Location  
= Year  
combinations of interconnects between V (pin 7) and V (pin 8)  
EF  
CF  
WL, L = Wafer Lot  
Y, YY  
W, WW = Work Week  
G
for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input  
levels, leave V and V open. For ECL operation, short V and  
CF  
EF  
CF  
= Pb−Free Package  
V
(Pins 7 and 8). For LVTTL level operation, connect a 1.5 V  
EF  
supply reference to V and leave open V pin. The 1.5 V reference  
CF  
EF  
voltage to V pin can be accomplished by placing a 2.2 kW resistor  
*For additional marking information, refer to  
Application Note AND8002/D.  
CF  
between V and V for a 3.3 V power supply.  
CF  
EE  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single−ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 15 of this data sheet.  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
BB  
The 100 Series contains temperature compensation.  
Features  
• Maximum Input Clock Frequency >1.2 GHz Typical  
• Programmable Range: 0 ns to 10 ns  
• Delay Range: 2.2 ns to 12.2 ns  
• 10 ps Increments  
• IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels  
• A Logic High on the EN Pin Will Force Q to Logic Low  
• D[10:0] Can Select Either LVPECL, LVCMOS, or  
LVTTL Input Levels  
• V Output Reference Voltage  
• PECL Mode Operating Range:  
BB  
• These are Pb−Free Devices  
V
CC  
= 3.0 V to 3.6 V with V = 0 V  
EE  
• NECL Mode Operating Range:  
= 0 V with V = −3.0 V to −3.6 V  
V
CC  
EE  
©
Semiconductor Components Industries, LLC, 2008  
1
Publication Order Number:  
September, 2008 − Rev. 1  
MC100EP195B/D  
1234567...17

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MC100EP195BFAG 替代型号

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