5秒后页面跳转
捷配首页

Datasheet > 驱动程序和接口 > 线路驱动器或接收器> MC100EP16VCDTG
MC100EP16VCDTG PDF预览

MC100EP16VCDTG

更新时间： 2024-09-29 05:22:27
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器
页数 文件大小 规格书
11页 156K
描述
3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output

阅读下载

中文翻译

获取价格

MC100EP16VCDTG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：TSSOP, TSSOP8,.19针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：7.88Samacsys Description：NULL
其他特性：CAN ALSO OPERATE WITH -3V TO -5.5V SUPPLY IN NECL MODE差分输出：YES
驱动器位数：1高电平输入电流最大值：0.00015 A
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：GENERAL PURPOSEJESD-30 代码：S-PDSO-G8
JESD-609代码：e3长度：3 mm
湿度敏感等级：3标称负供电电压：-4.5 V
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP8,.19封装形状：SQUARE
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：-4.5 V认证状态：Not Qualified
最大接收延迟：0.4 ns接收器位数：1
座面最大高度：1.1 mm子类别：Line Driver or Receivers
最大压摆率：38 mA最大供电电压：5.5 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：ECL
温度等级：INDUSTRIAL端子面层：Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
最大传输延迟：0.4 ns宽度：3 mm

MC100EP16VCDTG 数据手册

 浏览型号MC100EP16VCDTG的Datasheet PDF文件第2页浏览型号MC100EP16VCDTG的Datasheet PDF文件第3页浏览型号MC100EP16VCDTG的Datasheet PDF文件第4页浏览型号MC100EP16VCDTG的Datasheet PDF文件第5页浏览型号MC100EP16VCDTG的Datasheet PDF文件第6页浏览型号MC100EP16VCDTG的Datasheet PDF文件第7页 
MC100EP16VC  
3.3Vꢀ/ꢀ5VꢁECL Differential  
Receiver/Driver with High  
Gain and Enable Output  
Description  
http://onsemi.com  
MARKING DIAGRAMS*  
The EP16VC is a differential receiver/driver. The device is  
functionally equivalent to the EP16 and LVEP16 devices but with high  
gain and enable output.  
The EP16VC provides an EN input which is synchronized with the  
data input (D) signal in a way that provides glitchless gating of the  
QHG and QHG outputs.  
When the EN signal is LOW, the input is passed to the outputs and  
the data output equals the data input. When the data input is HIGH and  
8
KEP66  
ALYW  
G
SOIC−8  
D SUFFIX  
CASE 751  
8
1
1
1
EN goes HIGH, it will force the Q LOW and the Q HIGH on the  
HG  
HG  
next negative transition of the data input. If the data input is LOW  
when the EN goes HIGH, the next data transition to a HIGH is ignored  
8
1
TSSOP−8  
DT SUFFIX  
CASE 948R  
KP66  
8
and Q remains LOW and Q remains HIGH. The next positive  
HG  
HG  
ALYWG  
transition of the data input is not passed on to the data outputs under  
these conditions. The Q and Q outputs remain in their disabled  
G
HG  
HG  
state as long as the EN input is held HIGH. The EN input has no  
influence on the Q output and the data input is passed on (inverted) to  
this output whether EN is HIGH or LOW. This configuration is ideal  
for crystal oscillator applications where the oscillator can be free  
running and gated on and off synchronously without adding extra  
counts to the output.  
DFN8  
MN SUFFIX  
CASE 506AA  
1
4
The V /D pin is internally dedicated and available for differential  
A
L
Y
W
M
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Date Code  
= Pb−Free Package  
BB  
interconnect. V /D may rebias AC coupled inputs. When used,  
BB  
decouple V /D and V via a 0.01 mF capacitor and limit current  
BB  
CC  
sourcing or sinking to 1.5 mA. When not used, V /D should be left  
BB  
open.  
The 100 Series contains temperature compensation.  
(Note: Microdot may be in either location)  
Features  
*For additional marking information, refer to  
Application Note AND8002/D.  
• 310 ps Typical Prop Delay Q,  
380 ps Typical Prop Delay QHG, QHG  
• Gain > 200  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
• Maximum Frequency > 3 GHz Typical  
• PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
CC  
with V = −3.0 V to −5.5 V  
EE  
• Open Input Default State  
• Q Output Will Default LOW with D Inputs Open or at V  
HG  
EE  
• V Output  
BB  
• Pb−Free Packages are Available  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 − Rev. 5  
MC10EP16VC/D  
1234567...11

中文翻译

下载PDF

MC100EP16VCDTG 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP16VCDTR2G ONSEMI

完全替代

 3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output
MC100EP16VCDG ONSEMI

完全替代

 3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output
MC100EP16VCDTR2 ONSEMI

完全替代

 3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output

与MC100EP16VCDTG相关器件

型号 品牌 获取价格 描述 数据表
MC100EP16VCDTR2 ONSEMI

获取价格

 		3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output
MC100EP16VCDTR2G ONSEMI

获取价格

 		3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output
MC100EP16VCMNR4 ONSEMI

获取价格

 		3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output
MC100EP16VCMNR4G ONSEMI

获取价格

 		3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output
MC100EP16VS ONSEMI

获取价格

 		3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
MC100EP16VSD ONSEMI

获取价格

 		3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
MC100EP16VSDG ONSEMI

获取价格

 		3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
MC100EP16VSDR2 ONSEMI

获取价格

 		3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
MC100EP16VSDR2G ONSEMI

获取价格

 		3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
MC100EP16VSDT ONSEMI

获取价格

 		LINE TRANSCEIVER, PDSO8, TSSOP-8

与MC100EP16VCDTG相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证