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MC100EP16VC PDF预览

MC100EP16VC

更新时间: 2024-09-28 21:54:15
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器
页数 文件大小 规格书
10页 76K
描述
3.3V / 5V ECL Differential Receiver/Driver with High Gain and Enable Output

MC100EP16VC 数据手册

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MC100EP16VC  
3.3V / 5VꢀECL Differential  
Receiver/Driver with High  
Gain and Enable Output  
The EP16VC is a differential receiver/driver. The device is  
functionally equivalent to the EP16 and LVEP16 devices but with high  
gain and enable output.  
http://onsemi.com  
The EP16VC provides an EN input which is synchronized with the  
data input (D) signal in a way that provides glitchless gating of the  
QHG and QHG outputs.  
MARKING DIAGRAMS*  
When the EN signal is LOW, the input is passed to the outputs and  
the data output equals the data input. When the data input is HIGH and  
EN goes HIGH, it will force the Q LOW and the Q HIGH on the  
8
1
8
KEP66  
ALYW  
HG  
HG  
1
next negative transition of the data input. If the data input is LOW  
when the EN goes HIGH, the next data transition to a HIGH is ignored  
and Q remains LOW and Q remains HIGH. The next positive  
SO−8  
D SUFFIX  
CASE 751  
HG  
HG  
transition of the data input is not passed on to the data outputs under  
these conditions. The Q and Q outputs remain in their disabled  
HG  
HG  
8
1
state as long as the EN input is held HIGH. The EN input has no  
influence on the Q output and the data input is passed on (inverted) to  
this output whether EN is HIGH or LOW. This configuration is ideal  
for crystal oscillator applications where the oscillator can be free  
running and gated on and off synchronously without adding extra  
counts to the output.  
8
KP66  
ALYW  
1
TSSOP−8  
DT SUFFIX  
CASE 948R  
The V /D pin is internally dedicated and available for differential  
BB  
K = MC100  
A = Assembly Location  
L = Wafer Lot  
Y = Year  
W = Work Week  
interconnect. V /D may rebias AC coupled inputs. When used,  
BB  
decouple V /D and V via a 0.01 mF capacitor and limit current  
BB  
CC  
sourcing or sinking to 1.5 mA. When not used, V /D should be left  
BB  
open.  
The 100 Series contains temperature compensation.  
*For additional information, see Application Note  
AND8002/D  
310 ps Typical Prop Delay Q, 380 ps Typical Prop Delay QHG, QHG  
Gain > 200  
Maximum Frequency > 3 GHz Typical  
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
ORDERING INFORMATION  
NECL Mode Operating Range: V = 0 V  
CC  
Device  
Package  
Shipping  
with V = −3.0 V to −5.5 V  
EE  
MC100EP16VCD  
SO−8  
98 Units/Rail  
Open Input Default State  
MC100EP16VCDR2  
MC100EP16VCDT  
SO−8  
2500 Tape & Reel  
100 Units/Rail  
Q Output Will Default LOW with D Inputs Open or at V  
HG  
EE  
V Output  
BB  
TSSOP−8  
MC100EP16VCDTR2 TSSOP−8 2500 Tape & Reel  
Semiconductor Components Industries, LLC, 2003  
1
Publication Order Number:  
September, 2003− Rev. 2  
MC100EP16VC/D  

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